Coverage Points 51Cross Coverage 53Transition Coverage . 53What Does 100 Percent Functional Coverage Mean? . 54Verification Language Technologies 55Assertions . . 57Simulated Assertions . 58Formal Assertion Proving 59Revision Control . . 61The Software Engineering Experience 62Configuration Management . 63Working with Releases 65Issue Tracking 66What Is an Issue? 67The Grapevine System 68The Post-It System . . 68The Procedural System 69Computerized System 69Metrics . 71Code-Related Metrics 71Quality-Related Metrics . . 73Interpreting Metrics . 74Summary 76CHAPTER 3 The Verification Plan 77The Role of the Verification Plan . . 78Specifying the Verification 78Defining First-Time Success . 79Levels of Verification . . 80Unit-Level Verification 81Block and Core Verification . 82ASIC and FPGA Verification 84System-Level Verification . 84Board-Level Verification . . 85Verification Strategies 86Verifying the Response 86From Specification to Features . 87Block-Level Features 90System-Level Features 91Table of Contentsviii Writing Testbenches using SystemVerilogError Types to Look For . . 91Prioritize . 92Design for Verification 93Directed Testbenches Approach 96Group into Testcases . 96From Testcases to Testbenches 98Verifying Testbenches 99Measuring Progress 100Coverage-Driven Random-Based Approach . . 101Measuring Progress 101From Features to Functional Coverage . . 103From Features to Testbench 105From Features to Generators 107Directed Testcases . . 109Summary 111CHAPTER 4 High-Level Modeling 113High-Level versus RTL Thinking . .113Contrasting the Approaches 115You Gotta Have Style! . .117A Question of Discipline . 117Optimize the Right Thing 118Good Comments Improve Maintainability 121Structure of High-Level Code . 122Encapsulation Hides Implementation Details . . 122Encapsulating Useful Subprograms . 125Encapsulating Bus-Functional Models 127Data Abstraction . 1302-state Data Types . 131Struct, Class . 131Union . . 134Arrays . . 139Queues . 141Associative Arrays . 143Files 145From High-Level to Physical-Level . 146Object-Oriented Programming 147Classes . 147Inheritance . . 153Writing Testbenches using SystemVerilog ixPolymorphism 156The Parallel Simulation Engine 159Connectivity, Time and Concurrency 160The Problems with Concurrency . 160Emulating Parallelism on a Sequential Processor 162The Simulation Cycle 163Parallel vs. Sequential . . 169Fork/Join Statement 170The Difference Between Driving and Assigning . 173Race Conditions . . 176Read/Write Race Conditions 177Write/Write Race Conditions 180Initialization Races . 182Guidelines for Avoiding Race Conditions . 183Semaphores . . 184Portability Issues 186Events from Overwritten Scheduled values 186Disabled Scheduled values . 187Output Arguments on Disabled Tasks 188Non-Re-Entrant Tasks 188Static vs. Automatic Variables . . 193Summary . . 196CHAPTER 5 Stimulus and Response 197Reference Signals 198Time Resolution Issues . . 199Aligning Signals in Delta-Time . . 201Clock Multipliers . . 203Asynchronous Reference Signals 205Random Generation of Reference Signal Parameters 206Applying Reset 208Simple Stimulus . 212Applying Synchronous Data values . 212Abstracting Waveform Generation . . 214Simple Output 216Visual Inspection of Response 217Producing Simulation Results 217Minimizing Sampling 219Visual Inspection of Waveforms . 220Table of Contentsx Writing Testbenches using SystemVerilogSelf-Checking Testbenches . 221Input and Output Vectors 221Golden Vectors 222Self-Checking Operations 224Complex Stimulus 227Feedback Between Stimulus and Design . 228Recovering from Deadlocks 228Asynchronous Interfaces . 231Bus-Functional Models 234CPU Transactions . . 234From Bus-Functional Tasks to Bus-Functional Model 236Physical Interfaces . 238Configurable Bus-Functional Models 243Response Monitors 246Autonomous Monitors 249Slave Generators . . 253Multiple Possible Transactions . . 255Transaction-Level Interface 258Procedural Interface vs Dataflow Interface 259What is a Transaction? . . 263Blocking Transactions . . 265Nonblocking Transactions . 265Split Transactions . . 267Exceptions 270Summary . . 278CHAPTER 6 Architecting Testbenches 279Verification Harness . . 280Design Configuration . 284Abstracting Design Configuration . . 285Configuring the Design . . 288Random Design Configuration . . 290Self-Checking Testbenches 292Hard Coded Response . . 294Data Tagging 295Reference Models . . 297Transfer Function . . 299Scoreboarding 300Integration with the Transaction Layer . . 302Writing Testbenches using SystemVerilog xiDirected Stimulus 304Random Stimulus . 307Atomic Generation . 307Adding Constraints . 312Constraining Sequences . 316Defining Random Scenarios 320Defining Procedural Scenarios . 322System-Level Verification Harnesses . . 327Layered Bus-Functional Models . 328Summary . . 331CHAPTER 7 Simulation Management 333Transaction-Level Models 333Transaction-Level versus Synthesizable Models 334Example of Transaction-Level Modeling . 335Characteristics of a Transaction-Level Model . . 337Modeling Reset 341Writing Good Transaction-Level Models . 342Transaction-Level Models Are Faster 347The Cost of Transaction-Level Models 348The Benefits of Transaction-Level Models 349Demonstrating Equivalence 351Pass or Fail? 352Managing Simulations . 355Configuration Management 355Avoiding Recompilation or SDF Re-Annotation . 358Output File Management 361Seed Management . . 364Regression . 365Running Regressions 366Regression Management . 367Summary . . 370APPENDIX A Coding Guidelines 371File Structure 372Filenames 375Style Guidelines . . 376Table of Contentsxii Writing Testbenches using SystemVerilogComments 376Layout . . 378Structure 380Debugging 383Naming Guidelines 384Capitalization 384Identifiers 386Constants 389Portability Guidelines . 391APPENDIX B Glossary 397Index 401