CADENCE SIP DIGITAL LAYOUTWhile system-in-package (SiP) design allows electronics makers to pack morefunctionality into a smaller footprint, it often involves highly complex combinations,such as stacked wirebond die, wirebond die stacked on flip-chip die, direct die-to-die attachment, and others. CadenceSiP Digital Layout addresses this complexityby providing a complete constraint- and rules-driven package substrate layoutenvironment that supports all packaging methods, including PGA, BGA, micro-BGA,chip scale, as well as flip-chip and wirebond attach methods.