The DSSHA1 coprocessor with 64-byte RAM is a synthesizableregister transfer level (RTL) implementation ofthe FIPS 180-3 Secure Hash Algorithm (SHA-1), eliminatingthe need to develop software to perform the complexSHA-1 computation required for authenticatingSHA-1 devices. The DSSHA1 can compute SHA-1 messageauthentication codes (MACs) for use with MaximSHA-1 devices, such as the DS1963S, DS1961S,DS28E10, DS28E02, DS2460, DS28CN01, andDS28E01-100. The device can output the 20-byte MACresult from registers required for comparison againstSHA-1 slave devices. When incorporated into a design,DSSHA1 also provides an offloading function, relieving amicrocontroller of performing the SHA-1 computation.