These positive-edge triggered flip-flops utilize TTL circuitry toimplement D-type flip-flop logic. All have a direct clear input,and the quad (175) version features complementary outputsfrom each flip-flop.Information at the D inputs meeting the setup and hold timerequirements is transferred to the Q outputs on thepositive-going edge of the clock pulse. Clock triggering occursat a particular voltage level and is not directly related tothe transition time of the positive-going pulse. When theclock input is at either the high or low level, the D input signalhas no effect at the output.