CHAPTER 1GUIDE TO THIS MANUAL1.1 MANUAL CONTENTS.... 1-11.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY .... 1-31.3 RELATED DOCUMENTS . 1-51.3.1 Data Sheet ....1-61.3.2 Application Notes .......1-61.4 CUSTOMER SERVICE... 1-71.4.1 How to Use Intel's FaxBack Service .1-71.4.2 How to Use Intel's Application BBS ..1-81.4.3 How to Find the Latest ApBUILDER Files and Hypertext Manuals andData Sheets on the BBS ......1-9CHAPTER 2ARCHITECTURAL OVERVIEW2.1 8XC251SB CORE... 2-42.1.1 CPU ....2-42.1.2 Clock and Reset Unit .2-52.1.3 Interrupt Handler 2-62.1.4 On-chip Code Memory .2-62.1.5 On-chip RAM 2-72.2 ON-CHIP PERIPHERALS. 2-72.2.1 Timer/Counters and Watchdog Timer ....2-72.2.2 Programmable Counter Array (PCA) 2-72.2.3 Serial I/O Port ....2-8CHAPTER 3ADDRESS SPACES3.1 ADDRESS SPACES FOR MCS® 251 MICROCONTROLLERS . 3-13.1.1 Compatibility with the MCS® 51 Architecture .3-23.2 THE 8XC251SB MEMORY SPACE....... 3-53.2.1 On-chip General-purpose Data RAM 3-63.2.2 On-chip Code Memory (87C251SB/83C251SB) ......3-63.2.2.1 Accessing On-chip Code Memory in Region 00: .3-63.2.3 External Memory 3-83.3 THE 8XC251SB REGISTER FILE. 3-83.3.1 Byte, Word, and Dword Registers .....3-83.3.2 Dedicated Registers .3-10CONTENTSiv3.3.2.1 Accumulator and B Register ..3-103.3.2.2 Extended Data Pointer, DPX .3-103.3.2.3 Extended Stack Pointer, SPX 3-113.4 SPECIAL FUNCTION REGISTERS (SFRS) .... 3-12CHAPTER 4PROGRAMMING4.1 BINARY MODE AND SOURCE MODE CONFIGURATIONS ... 4-14.1.1 Selecting Binary Mode or Source Mode .4-24.2 PROGRAMMING FEATURES OF THE MCS® 251 ARCHITECTURE .... 4-44.2.1 Data Types ....4-44.2.2 Register Notation .......4-44.2.3 Address Notation .......4-54.2.4 Addressing Modes .....4-54.3 DATA INSTRUCTIONS .. 4-64.3.1 Data Addressing Modes .......4-64.3.1.1 Register Addressing ...4-84.3.1.2 Immediate .4-84.3.1.3 Direct ...4-84.3.1.4 Indirect .4-94.3.1.5 Displacement ....4-94.3.2 Arithmetic Instructions 4-104.3.3 Logical Instructions ..4-114.3.4 Data Transfer Instructions ..4-114.4 BIT INSTRUCTIONS .... 4-124.4.1 Bit Addressing ..4-124.5 CONTROL INSTRUCTIONS .. 4-144.5.1 Addressing Modes for Control Instructions ..4-144.5.2 Conditional Jumps ...4-154.5.3 Unconditional Jumps 4-164.5.4 Calls and Returns ....4-164.6 PROGRAM STATUS WORDS .... 4-17CHAPTER 5INTERRUPT SYSTEM5.1 OVERVIEW ....... 5-15.2 8XC251SB INTERRUPT SOURCES..... 5-35.2.1 External Interrupts ......5-35.2.2 Timer Interrupts ..5-45.3 PROGRAMMABLE COUNTER ARRAY (PCA) INTERRUPT.... 5-55.4 SERIAL PORT INTERRUPT..... 5-55.5 INTERRUPT ENABLE .... 5-55.6 INTERRUPT PRIORITIES 5-65.7 INTERRUPT PROCESSING .... 5-95.7.1 Minimum Fixed Interrupt Time 5-105.7.2 Variable Interrupt Parameters .5-105.7.2.1 Response Time Variables .....5-105.7.2.2 Computation of Worst-case Latency With Variables .5-125.7.2.3 Latency Calculations 5-135.7.2.4 Blocking Conditions ..5-145.7.2.5 Interrupt Vector Cycle ....5-145.7.3 ISRs in Process .......5-15CHAPTER 6INPUT/OUTPUT PORTS6.1 INPUT/OUTPUT PORT OVERVIEW..... 6-16.2 I/O CONFIGURATIONS.. 6-26.3 PORT 1 AND PORT 3 .... 6-26.4 PORT 0 AND PORT 2 .... 6-26.5 READ-MODIFY-WRITE INSTRUCTIONS.. 6-56.6 QUASI-BIDIRECTIONAL PORT OPERATION... 6-56.7 PORT LOADING 6-76.8 EXTERNAL MEMORY ACCESS... 6-7CHAPTER 7TIMER/COUNTERS AND WATCHDOG TIMER7.1 TIMER/COUNTER OVERVIEW 7-17.2 TIMER/COUNTER OPERATION... 7-17.3 TIMER 0... 7-47.3.1 Mode 0 (13-bit Timer) 7-47.3.2 Mode 1 (16-bit Timer) 7-57.3.3 Mode 2 (8-bit Timer With Auto-reload) ...7-57.3.4 Mode 3 (Two 8-bit Timers) ...7-57.4 TIMER 1... 7-67.4.1 Mode 0 (13-bit Timer) 7-97.4.2 Mode 1 (16-bit Timer) 7-97.4.3 Mode 2 (8-bit Timer with Auto-reload) ....7-97.4.4 Mode 3 (Halt) 7-97.5 TIMER 0/1 APPLICATIONS...... 7-97.5.1 Auto-load Setup Example ....7-97.5.2 Pulse Width Measurements ....7-107.6 TIMER 2. 7-107.6.1 Capture Mode ..7-117.6.2 Auto-reload Mode ....7-127.6.2.1 Up Counter Operation ...7-127.6.2.2 Up/Down Counter Operation .7-137.6.3 Baud Rate Generator Mode ....7-147.6.4 Clock-out Mode 7-147.7 WATCHDOG TIMER .... 7-167.7.1 Des cription ..7-167.7.2 Using the WDT .7-187.7.3 WDT During Idle Mode ......7-187.7.4 WDT During PowerDown ...7-18CHAPTER 8PROGRAMMABLE COUNTER ARRAY8.1 PCA DEs criptION....... 8-18.2 PCA TIMER/COUNTER.. 8-28.3 PCA COMPARE/CAPTURE MODULES .... 8-58.3.1 16-bit Capture Mode ..8-58.3.2 Compare Modes 8-78.3.3 16-bit Software Timer Mode .8-78.3.4 High-speed Output Mode .....8-88.3.5 PCA Watchdog Timer Mode 8-98.3.6 Pulse Width Modulation Mode 8-11CHAPTER 9SERIAL I/O PORT9.1 OVERVIEW ....... 9-19.2 MODES OF OPERATION. 9-49.2.1 Synchronous Mode (Mode 0) ....9-49.2.1.1 Transmission (Mode 0) ....9-49.2.1.2 Reception (Mode 0) ....9-59.2.2 Asynchronous Modes (Modes 1, 2, and 3) ....9-69.2.2.1 Transmission (Modes 1, 2, 3) ..9-69.2.2.2 Reception (Modes 1, 2, 3) .......9-69.3 FRAMING BIT ERROR DETECTION (MODES 1, 2, AND 3).... 9-79.4 MULTIPROCESSOR COMMUNICATION (MODES 2 AND 3) .. 9-79.5 AUTOMATIC ADDRESS RECOGNITION.. 9-79.5.1 Given Address ...9-89.5.2 Broadcast Address .....9-99.5.3 Reset Addresses ......9-109.6 BAUD RATES.. 9-109.6.1 Baud Rate for Mode 0 9-109.6.2 Baud Rates for Mode 2 ......9-109.6.3 Baud Rates for Modes 1 and 3 .......9-109.6.3.1 Timer 1 Generated Baud Rates (Modes 1 and 3) .....9-119.6.3.2 Selecting Timer 1 as the Baud Rate Generator 9-119.6.3.3 Timer 2 Generated Baud Rates (Modes 1 and 3) .....9-129.6.3.4 Selecting Timer 2 as the Baud Rate Generator 9-12CHAPTER 10MINIMUM HARDWARE SETUP10.1 MINIMUM HARDWARE SETUP.. 10-110.2 ELECTRICAL ENVIRONMENT... 10-210.2.1 Power and Ground Pins .....10-210.2.2 Unused Pins 10-210.2.3 Noise Considerations .10-210.3 CLOCK SOURCES....... 10-310.3.1 On-chip Oscillator (Crystal) 10-310.3.2 On-chip Oscillator (Ceramic Resonator) ......10-410.3.3 External Clock ..10-410.4 RESET... 10-510.4.1 Externally Initiated Resets .10-610.4.2 WDT Initiated Resets .10-610.4.3 Reset Operation .......10-610.4.4 Power-on Reset .......10-7CHAPTER 11SPECIAL OPERATING MODES11.1 GENERAL 11-111.2 POWER CONTROL REGISTER . 11-111.2.1 Serial I/O Control Bits 11-111.2.2 Power Off Flag .11-111.3 IDLE MODE..... 11-411.3.1 Entering Idle Mode ...11-411.3.2 Exiting Idle Mode .....11-511.4 POWERDOWN MODE. 11-511.4.1 Entering Powerdown Mode 11-611.4.2 Exiting Powerdown Mode ..11-611.5 ON-CIRCUIT EMULATION (ONCE) MODE ..... 11-711.5.1 Entering ONCE Mode 11-711.5.2 Exiting ONCE Mode .11-7CHAPTER 12EXTERNAL MEMORY INTERFACE12.1 EXTERNAL MEMORY INTERFACE SIGNALS 12-112.2 CONFIGURING THE EXTERNAL MEMORY INTERFACE..... 12-212.2.1 Page Mode and Nonpage Mode (PAGE Bit) .12-312.2.2 RD#, PSEN#, and the Number of External Address Pins (Bits RD1:0) .....12-312.2.2.1 Sixteen External Address Bits and a Single Read Signal(RD1 = 1, RD0 = 0) ..12-412.2.2.2 Seventeen External Address Bits and a Single Read Signal(RD1 = 0, RD0 = 1) ..12-412.2.2.3 Sixteen External Address Bits and Two Read Signals(RD1 = 1, RD0 = 1) ..12-512.2.3 Wait States (WSA, WSB, XALE) .....12-612.2.4 Mapping On-chip Code Memory to Data Memory (87C251SB/83C251SB) ...12-712.3 EXTERNAL BUS CYCLES..... 12-712.3.1 Inactive External Bus .12-712.3.2 Bus Cycle Definitions .12-812.3.3 Nonpage Mode Bus Cycles ....12-812.3.4 Page Mode Bus Cycles ....12-1012.4 WAIT STATES.... 12-1312.4.1 Extending PSEN#/RD#/WR# 12-1312.4.2 Extending ALE .......12-1412.5 PORT 0 AND PORT 2 STATUS 12-1512.5.1 Port 0 and Port 2 Pin Status in Nonpage Mode ...12-1512.5.2 Port 0 and Port 2 Pin Status in Page Mode .12-1612.6 EXTERNAL MEMORY DESIGN EXAMPLES. 12-1612.6.1 Nonpage Mode, 64 Kbytes External EPROM, 64 Kbytes External RAM .12-1612.6.1.1 An Application Requiring Fast Access to the Stack .12-1612.6.1.2 An Application Requiring Fast Access to Data 12-1712.6.2 Nonpage Mode, 128 Kbytes External RAM .12-1912.6.3 Page Mode, 128 Kbytes External Flash .....12-2112.6.4 Page Mode, 64 Kbytes External EPROM, 64 Kbytes External RAM .......12-2112.6.5 Page Mode, 64 Kbytes External Flash, 32 Kbytes External RAM ....12-2212.7 EXTERNAL BUS AC TIMING SPECIFICATIONS.... 12-2412.7.1 Explanation of AC Symbols ..12-2812.7.2 AC Timing Definitions ......12-28CHAPTER 13PROGRAMMING AND VERIFYINGNONVOLATILE MEMORY13.1 GENERAL 13-113.2 PROGRAMMING AND VERIFYING MODES... 13-213.3 GENERAL SETUP 13-313.4 OTPROM PROGRAMMING ALGORITHM....... 13-413.5 VERIFY ALGORITHM... 13-513.6 PROGRAMMABLE FUNCTIONS 13-513.6.1 On-chip Code Memory .......13-513.6.2 Configuration Bytes ..13-613.6.3 Lock Bit System .......13-913.6.4 Encryption Array ....13-1013.6.5 Signature Bytes ......13-1013.7 VERIFYING THE 83C251SB (ROM) . 13-1013.8 VERIFYING THE 80C251SB (ROMLESS)..... 13-11APPENDIX AINSTRUCTION SET REFERENCEA.1 NOTATION FOR INSTRUCTION OPERANDS. A-2A.2 OPCODE MAP AND SUPPORTING TABLES .. A-4A.3 INSTRUCTION SET SUMMARY A-11A.3.1 Execution Times for Instructions that Access the Port SFRs ...... A-11A.3.2 Instruction Summaries ..... A-14A.4 INSTRUCTION DEs criptIONS ....... A-26FIGURESFigure Page2-1 Functional Block Diagram of the 8XC251SB.....2-22-2 The CPU.2-52-3 8XC251SB Timing.2-63-1 Address Spaces for MCS® 251 Microcontrollers.3-13-2 Address Spaces for the MCS® 51 Architecture.3-33-3 Address Space Mappings MCS® 51 Architecture to MCS® 251 Architecture.3-43-4 8XC251SB Memory Space .....3-73-5 The Register File ...3-93-6 Dedicated Registers in the Register File and their Corresponding SFRs......3-114-1 Binary Mode Opcode Map.......4-34-2 Source Mode Opcode Map .....4-34-3 Program Status Word Register...4-194-4 Program Status Word 1 Register4-205-1 Interrupt Control System .5-25-2 Interrupt Enable Register 5-65-3 Interrupt Priority High Register 5-85-4 Interrupt Priority Low Register.5-85-5 The Interrupt Process....5-95-6 Response Time Example #1 .5-115-7 Response Time Example #2 .5-126-1 Port 1 and Port 3 Structure......6-36-2 Port 0 Structure 6-36-3 Port 2 Structure 6-46-4 Internal Pullup Configurations .6-67-1 Basic Logic of the Timer/Counters .......7-27-2 Timer 0/1 in Mode 0 and Mode 1 .7-47-3 Timer 0/1 in Mode 2, Auto-Reload7-57-4 Timer 0 in Mode 3, Two 8-bit Timers....7-67-5 TMOD: Timer/Counter Mode Control Register ..7-77-6 TCON: Timer/Counter Control Register ....7-87-7 Timer 2: Capture Mode .7-117-8 Timer 2: Auto Reload Mode (DCEN = 0).7-127-9 Timer 2: Auto Reload Mode (DCEN = 1).7-137-10 Timer 2: Clock Out Mode.......7-157-11 T2MOD: Timer 2 Mode Control Register.7-167-12 T2CON: Timer 2 Control Register ......7-178-1 Programmable Counter Array..8-38-2 PCA 16-bit Capture Mode .......8-68-3 PCA Software Timer and High-speed Output Modes..8-88-4 PCA Watchdog Timer Mode..8-108-5 PCA 8-bit PWM Mode .8-118-6 PWM Variable Duty Cycle .....8-128-7 CMOD: PCA Timer/Counter Mode Register....8-138-8 CCON: PCA Timer/Counter Control Register..8-14Figure Page8-9 CCAPMx: PCA Compare/Capture Module Mode Registers...8-169-1 Serial Port Block Diagram .......9-29-2 Serial Port Special Function Register...9-39-3 Mode 0 Timing..9-59-4 Data Frame (Modes 1, 2, and 3) ..9-69-5 Timer 2 in Baud Rate Generator Mode ...9-1310-1 Minimum Setup ...10-110-2 CHMOS On-chip Oscillator....10-310-3 External Clock Connection ....10-410-4 External Clock Drive Waveforms10-510-5 Reset Timing Sequence 10-811-1 Power Control (PCON) Register.11-211-2 Idle and Powerdown Clock Control ....11-312-1 Internal and External Memory Spaces for RD1 = 1, RD0 = 0.12-412-2 Internal and External Memory Spaces for RD1 = 0, RD0 = 1.12-512-3 Internal and External Memory Spaces for RD1 = 1, RD0 = 1.12-612-4 External Code Fetch or Data Read Bus Cycle (Nonpage Mode) .....12-912-5 External Write Bus Cycle (Nonpage Mode).....12-912-6 Bus Structure in Nonpage Mode and Page Mode...12-1012-7 External Code Fetch Bus Cycle (Page Mode).12-1112-8 External Data Read Bus Cycle (Page Mode) 12-1212-9 External Write Bus Cycle (Page Mode) .12-1212-10 External Code Fetch or Data Read Bus Cycle with One PSEN#/RD#Wait State (Nonpage Mode) 12-1312-11 External Write Bus Cycle with One WR# Wait State (Nonpage Mode) .......12-1412-12 External Code Fetch or Data Read Bus Cycle with One ALE Wait State(Nonpage Mode) .......12-1412-13 80C251SB in Nonpage Mode with External EPROM and RAM.....12-1712-14 The Memory Space for the Systems of Figure 12-13 and Figure 12-18 .....12-1812-15 87C251SB/83C251SB in Nonpage Mode with 128 Kbytes of External RAM...12-1912-16 The Memory Space for the System of Figure 12-1512-2012-17 80C251SB in Page Mode with External Flash.12-2112-18 80C251SB in Page Mode with External EPROM and RAM .12-2212-19 80C251SB in Page Mode with External Flash and RAM......12-2312-20 The Memory Space for the System of Figure 12-1912-2412-21 External Bus Cycles for Data/Instruction Read and Data Write inNonpage Mode..12-2512-22 External Bus Cycles for Data Read and Data Write in Page Mode12-2612-23 External Bus Cycles for Instruction Read in Page Mode......12-2713-1 Setup for Programming and Verifying 13-313-2 OTPROM Programming Waveforms..13-413-3 Configuration Byte 0....13-713-4 Configuration Byte 1....13-813-5 OTPROM Timing.......13-112-1 Summary of 8XC251SB Features 2-43-1 Address Mappings.3-43-2 Register Bank Selection 3-83-3 Dedicated Registers in the Register File and their Corresponding SFRs......3-123-4 8XC251SB SFR Map and Reset values .3-133-5 Core SFRs......3-143-6 I/O Port SFRs .3-143-7 Serial I/O SFRs ...3-153-8 Timer/Counter and Watchdog Timer SFRs .....3-153-9 Programmable Counter Array (PCA) SFRs.....3-154-1 Examples of Opcodes in Binary and Source Modes ...4-24-2 Data Types .......4-44-3 Notation for Byte Registers, Word Registers, and Dword Registers ..4-54-4 Addressing Modes for Data Instructions in the MCS® 51 Architecture ...4-64-5 Addressing Modes for Data Instructions in the MCS® 251 Architecture .4-74-6 Bit-addressable Locations .....4-134-7 Addressing Two Sample Bits.4-134-8 Addressing Modes for Bit Instructions4-144-9 Addressing Modes for Control Instructions......4-154-10 Compare-conditional Jump Instructions ..4-164-11 The Effects of Instructions on the PSW and PSW1 Flags......4-185-1 Interrupt System Pin Signals ...5-15-2 Interrupt System Special Function Registers ....5-35-3 Interrupt Control Matrix..5-45-4 Level of Priority.5-75-5 Interrupt Priority Within Level ..5-75-6 Interrupt Latency Variables ...5-135-7 Actual vs. Predicted Latency Calculations.......5-136-1 Input/Output Port Pin Des criptions .......6-16-2 Instructions for External Data Moves....6-87-1 Timer/Counter and Watchdog Timer SFRs .......7-27-2 External Signals ....7-37-3 Timer 2 Modes of Operation..7-158-1 PCA Special Function Registers (SFRs) ...8-48-2 External Signals ....8-48-3 PCA Module Modes ....8-159-1 Serial Port Signals.9-19-2 Serial Port Special Function Registers.9-29-3 Summary of Baud Rates .......9-109-4 Timer 1 Generated Baud Rates for Serial I/O Modes 1 and 39-129-5 Selecting the Baud Rate Generator(s) ....9-139-6 Timer 2 Generated Baud Rates .9-1411-1 Pin Conditions in Various Modes11-312-1 External Memory Interface Signals.....12-112-2 Configuration Bits RD1:0.......12-312-3 Wait State Selection ....12-612-4 Bus Cycle Definitions (No Wait States) ...12-812-5 Port 0 and Port 2 Pin Status In Normal Operating Mode......12-1512-6 AC Timing Symbol Definitions..12-2812-7 AC Timing Definitions for Specifications on the 8XC251SB.12-2912-8 AC Timing Definitions for Specifications on the Memory System...12-3013-1 Programming and Verifying Modes ....13-213-2 Configuration Byte values for 80C251SB and 80C251SB-1613-913-3 Lock Bit Function.13-913-4 Contents of the Signature Bytes.......13-1013-5 OTPROM Timing Definitions ....13-12A-1 Notation for Register Operands... A-2A-2 Notation for Direct Addresses. A-3A-3 Notation for Immediate Addressing ..... A-3A-4 Notation for Bit Addressing..... A-3A-5 Notation for Destinations in Control Instructions A-3A-6 Instructions for MCS® 51 Microcontrollers ....... A-4A-7 New Instructions for the MCS® 251 Architecture ....... A-5A-8 Data Instructions .. A-6A-9 High Nibble, Byte 0 of Data Instructions... A-6A-10 Bit Instructions. A-7A-11 Byte 1 (High Nibble) for Bit Instructions... A-7A-12 PUSH/POP Instructions . A-8A-13 Control Instructions ..... A-8A-14 Displacement/Extended MOVs.... A-9A-15 INC/DEC A-10A-16 Encoding for INC/DEC . A-10A-17 Shifts ... A-10A-18 State Times to Access the Port SFRs .... A-12A-19 Summary of Add and Subtract Instructions.... A-14A-20 Summary of Compare Instructions.... A-15A-21 Summary of Increment and Decrement Instructions A-16A-22 Summary of Multiply, Divide, and Decimal-adjust Instructions A-16A-23 Summary of Logical Instructions ....... A-17A-24 Summary of Move Instructions.. A-19A-25 Summary of Exchange, Push, and Pop Instructions A-22A-26 Summary of Bit Instructions.. A-23A-27 Summary of Control Instructions ....... A-24A-28 Flag Symbols. A-26B-1 Signals Arranged by Functional Categories ..... B-1B-2 Des cription of Columns of Table B-3... B-2B-3 Signal Des criptions....... B-2C-1 8XC251SB Special Function Registers (SFRs)C-1