The CD4034BM/CD4034BC is an 8-bit CMOS static shiftregister with two parallel bidirectional data ports (A and B)which, when combined with serial shifting operations, canbe used to (1) bidirectionally transfer parallel data betweentwo buses, (2) convert serial data to parallel form and directthem to either of two buses, (3) store (recirculate) paralleldata, or (4) accept parallel data from either of two busesand convert them to serial form. These operations are controlledby five control inputs:A ENABLE (AE): ``A'' data port is enabled only when AEis at logical ``1''. This allows the use of a common busfor multiple packages.A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B): This inputcontrols the direction of data flow. When at logical `'1'',data flows from port A to B (A is input, B is output).When at logical ``0'', the data flow direction is reversed.ASYNCHRONOUS/SYNCHRONOUS (A/S): When A/Sis at logical ``0'', data transfer occurs at positive transitionof the CLOCK. When A/S is at logical ``1'', datatransfer is independent of the CLOCK for parallel operation.In serial mode, A/S input is internally disabled suchthat operation is always synchronous. (Asynchronousserial operation is not possible.)PARALLEL/SERIAL (P/S): A logical ``1'' P/S input allowsdata transfer into the registers via A or B port (synchronousif A/S e logical ``0'', asynchronous if A/S elogical ``1''). A logical ``0'' P/S allows serial data totransfer into the register synchronously with the positivetransition of the CLOCK, independent of the A/S input.CLOCK: Single phase, enabled only in synchronousmode. (Either P/S e logical ``1'' and A/S e logical ``0''or P/S e logical ``0''.All register stages are D-type master-slave flip-flops withseparate master and slave clock inputs generated internallyto allow synchronous or asynchronous data transfer frommaster to slave.All inputs are protected against damage due to static dischargeby diode clamps to VDD and VSS.