The DS90CR285 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling)data streams. A phase-locked transmit clock is transmittedin parallel with the data streams over a fifth LVDS link.Every cycle of the transmit clock 28 bits of input data aresampled and transmitted. The DS90CR286 receiver convertsthe LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 66 MHz, 28 bitsof TTL data are transmitted at a rate of 462 Mbps per LVDSdata channel. Using a 66 MHz clock, the data throughput is1.848 Gbit/s (231 Mbytes/s).
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