Understanding the Effect of Clock Jitter on High Speed ADCs:Digitizing high speed signals to a high resolution requirescareful selection of a clock that will not compromise thesampling performance of the Analog to Digital Converter(ADC). In this article we hope to give the reader a betterunderstanding of clock jitter and how it affects theperformance of the high speed ADC.As an example we will highlight the latest high performanceADC from Linear Technology, the 16-bit, 160MspsLTC2209. This ADC exhibits a signal to noise ratio (SNR)of 77.4dB, with 100dB SFDR throughout much of thebaseband region. Like most high speed ADCs on themarket today, the LTC2209 uses a sample-and-hold (S&H)circuit that essentially takes a snapshot of the ADC inputat an instant in time. When the S&H switch is closed,the network at the input of the ADC is connected to thesample capacitor. At the instant the switch is openedone half clock cycle later, the voltage on the capacitoris recorded and held. Variation in the time at which theswitch is opened is known as aperture uncertainty, or jitter,and will result in an error voltage that is proportionalto the magnitude of the jitter and the input signal slew rate. In other words, the greater the input frequency and amplitude, the more susceptible you are to jitter on the clock source. Figure 1 demonstrates this relationship of slew rate proportional to jitter.