54LS173/DM74LS173ATRI-STATEÉ 4-Bit D-Type RegisterGeneral Des criptionThis four-bit register contains D-type flip-flops with totempoleTRI-STATEÉ outputs, capable of driving highly capacitiveor low-impedance loads. The high-impedance state andincreased high-logic-level drive provide these flip-flops withthe capability of driving the bus lines in a bus-organized systemwithout need for interface or pull-up components.Gated enable inputs are provided for controlling the entry ofdata into the flip-flops. When both data-enable inputs arelow, data at the D inputs are loaded into their respective flipflopson the next positive transition of the buffered clockinput. Gate output control inputs are also provided. Whenboth are low, the normal logic states of the four outputs areavailable for driving the loads or bus lines. The outputs aredisabled independently from the level of the clock by a highlogic level at either output control input. The outputs thenpresent a high impedance and neither load nor drive the busline. Detailed operation is given in the truth table.To minimize the possibility that two outputs will attempt totake a common bus to opposite logic levels, the output controlcircuitry is designed so that the average output disabletimes are shorter than the average output enable times.FeaturesY TRI-STATE outputs interface directly with system busY Gated output control lines for enabling or disabling theoutputsY Fully independent clock eliminates restrictions for operatingin one of two modes:Parallel loadDo nothing (hold)Y For application as bus buffer registers