I implemented 2Q cache strategy from paper "2Q: A Low Overhead High Performance Buffer Management Replacement Algorithm" written by Theodore Johnson and Dennis Shasha. It is written in VHDL and supports my FORTH-processor, which runs on a Spartan 3A DSP board from Xilinx. I think it can be adapted for other processors easily.

parameters, user defineable:

- blocksizeld ld of size of tagram

- ldways ld of number of tagrams (n-way associative)

- ldcachedwords ld of number of 32-bit words in one cacheline

defineable too:

- ldram ld of depth of cacheram

- ldqueuelength ld of depth of fifo (2Q strategy)

YOU have to redefine subtype RAMrange in global.vhd:

As example, Your RAM is 128 MB then

subtype RAMrange is natural range 26 downto 0;