The ADF4001 clock generator can be used to implement clocksources for PLLs that require very low noise, stable referencesignals. It consists of a low noise digital PFD (phase frequencydetector), a precision charge pump, a programmable referencedivider, and a programmable 13-bit N counter. In addition, the14-bit reference counter (R counter) allows selectable REFINfrequencies at the PFD input. A complete PLL (phase-lockedloop) can be implemented if the synthesizer is used with an externalloop filter and VCO (voltage controlled oscillator) orVCXO (voltage controlled crystal oscillator). The N minimumvalue of 1 allows flexibility in clock generation.