Abstract: A delay line can be used to build a clock fail detector circuit that can determine if a system clock frequency falls below, or rises above, a predetermined value. This application note explains how to use the precise time delay generated by the delay line to build a "window" around the clock time period to determine if it rises above or drops below a specified time period range. An example is given using the DS1000 (now obsolete and replaced with the DS1100). The application note is relevant for all delay lines and can be used as an example to build programmable clock fail detectors using programmable delay lines. Such circuits could be used not only in built-in-test but also in production testing applications.