UCLA Prof Razavi研究室的优秀高速高精度ADC设计论文，很有启发

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A 10bit 1GSs CMOS ADC with FOM 70 fJConversion Sedigheh Hashemi and Behzad Razavi Electrical Engineering Department University of California Los Angeles Abstract A pipelined ADC incorporates a precharged resistorladder DAC in a multibit frontend achieving fast settling and allowing calibration of both dynamic and static gain errors Using simple differential pairs with a gain of 5 as op amps and realized in 65nm CMOS technology the 10bit ADC consumes 36 mW at a sampling rate of 1 GHz and exhibit......