The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling)data streams. A phase-locked transmit clock is transmittedin parallel with the data streams over a fifth LVDS link.Every cycle of the transmit clock 28 bits of input data aresampled and transmitted. The DS90CR288A receiver convertsthe four LVDS data streams back into 28 bits ofLVCMOS/LVTTL data. At a transmit clock frequency of 85MHz, 28 bits of TTL data are transmitted at a rate of 595Mbps per LVDS data channel. Using a 85 MHz clock, thedata throughput is 2.38 Gbit/s (297.5 Mbytes/sec).