54LS195A/DM74LS195A4-Bit Parallel Access Shift RegisterGeneral Des criptionThis 4-bit register features parallel inputs, parallel outputs,J-K serial inputs, shift/load control input, and a direct overridingclear. All inputs are buffered to lower the input driverequirements. The registers have two modes of operation:Parallel (broadside) loadShift (in the direction QA toward QD)Parallel loading is accomplished by applying the four bits ofdata and taking the shift/load control input low. The data isloaded into the associated flip-flop and appears at the outputsafter the positive transition of the clock input. Duringloading, serial data flow is inhibited.Shifting is accomplished synchronously when the shift/loadcontrol input is high. Serial data for this mode is entered atthe J-K inputs. These inputs permit the first stage to performas a J-K, D, or T-type flip-flop as shown in the truth table.FeaturesY Synchronous parallel loadY Positive-edge-triggered clockingY Parallel inputs and outputs from each flip-flopY Direct overriding clearY J and K inputs to first stageY Complementary outputs from last stageY For use in high-performance:accumulators/processorsserial-to-parallel, parallel-to-serial convertersY Typical clock frequency 39 MHzY Typical power dissipation 70 mW