The DS90CR486 receiver converts eight Low Voltage DifferentialSignaling (LVDS) data streams back into 48 bits ofLVCMOS/LVTTL data. Using a 133MHz clock, the datathroughput is 6.384Gbit/s (798Mbytes/s).The multiplexing of data lines provides a substantial cable reduction.Long distance parallel single-ended buses typicallyrequire a ground wire per active signal (and have very limitednoise rejection capability). Thus, for a 48-bit wide data andone clock, up to 98 conductors are required. With this ChannelLink chipset as few as 19 conductors (8 data pairs, 1 clockpair and a minimum of one ground) are needed. This providesan 80% reduction in interconnect width, which provides a systemcost savings, reduces connector physical size and cost,and reduces shielding requirements due to the cables' smallerform factor.