A resolution-rate scalable ADC for micro-sensor net-works is described. Based on the successive approximation register(SAR) architecture, this ADC has two resolution modes: 12 bit and8 bit, and its sampling rate is scalable, at a constant figure-of-merit,from 0–100 kS/s and 0–200 kS/s, respectively. At the highest per-formance point (i.e., 12 bit, 100 kS/s), the entire ADC (includingdigital, analog, and reference power) consumes 25μW from a 1-Vsupply. The ADC\'s CMRR is enhanced by common-mode inde-pendent sampling and passive auto-zero reference generation. Theefficiency of the comparator is improved by an analog offset cali-brating latch, and the preamplifier settling time is relaxed by self-timing the bit-decisions. Prototyped in a 0.18μm, 5M2P CMOSprocess, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of65 dB (10.55 ENOB) and an SFDR of 71 dB. Its INL and DNL are0.68 LSB and 0.66 LSB, respectively.