The ADC is implemented in 16nm CMOS. The total analog area is 0.24mm2andthe digital equalizer occupies less than 0.1mm2(Fig. 27.6.7). At 4GS/s, the ADCconsumes 300mW, including 275mW from a 1.8V supply in which 120mW isdissipated by the input buffer, reference generation, clock generation and allinternal regulators, and 25mW consumed by digital equalizer from a 0.8V supply.Figure 27.6.5 shows the ADC output spectrums with 450MHz and 1900MHzinputs using analog skew correction. The ADC has a peak SFDR of 75dB and theSFDR at 1900MHz is 68dB. The SNDR is 60dB at 450MHz and 56dB at 1900MHz,which includes thermal and 1/f noise, distortion, clock jitter, and digital noise.The ADC noise level measured with a small input is -66dBFS. Figure 27.6.6 showsthe measured SNDR/SFDR versus input frequency and compares this ADC toseveral recently published ADCs with respect to SNDR, SFDR, Walden FOM andSchreier FOM, Based on the SNDR at Nyquist, it has a Walden FOM of145.5fJ/conv-step and a Schreier FOM of 154.2dB, while achieving the highestSNDR and SFDR among ADCs with sample rates above 2.5GS/s presented in thefigure.