TSMC_3_0_Design_flow_diagramTSMC Hierarchical Design Flow DiagramTSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.0Confidential-Security C1PrototypingHierarchical Timing ClosureFullchip VerificationNetlist, Timing Constraint, Sizebudgeting (PT) RC Correlation(FE->PC) full chip verification: IR analysis (Voltage Storm) DRC LVS (Calibre) Formal Verification (Formality, Verplex) xtalk (CeltIc)RC Correlation (StarRCXT->Apollo->FE)block frame view and pdb generation(APO) block preCTS implementation (PC): placement, timing optimization block timing model generationflattened prototyping (FE)floorplanning (FE) top preCTS implementation (PC): placement, timing optimization top level trial route (APO) top/block implementation (APO): CTS, track assign, SDF RC Correlation (APO->PC) b……