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标签： IC设计

1 CMOS Digital Design .............................................................................. 1

1.1 Design of CMOS SRAM Cell and Array ......................................... 1

1.1.1 Plan of SRAM Cell and Array .............................................. 1

1.1.2 Design of 6 Transistor SRAM Cell....................................... 2

1.1.3 Simulations of SRAM Cell ................................................... 2

1.1.4 Layout of SRAM Cell........................................................... 3

1.1.5 Design of SRAM Array ........................................................ 4

1.1.6 Simulation of SRAM Array .................................................. 4

1.2 Design of SRAM Chip Circuit Elements.......................................... 5

1.2.1 SRAM Chip Circuit Elements............................................... 5

1.2.2 Design of Complete SRAM Chip ......................................... 8

1.2.3 Simulations of Complete SRAM Chip.................................. 10

1.2.4 Delay Extraction for SRAM Chip Write/Read

Operation............................................................................... 10

1.2.5 Re-Design of SRAM Chip for Low Power

Consumption ......................................................................... 10

Appendix.................................................................................................... 12

References.................................................................................................. 15

2 FPGA Application Design ....................................................................... 17

2.1 Design of Direct Sequence-Spread Spectrum System...................... 18

2.1.1 PN Sequence Generator........................................................ 18

2.1.2 Transmitter for Direct Sequence-Spread

Spectrum System .................................................................. 21

2.1.3 Receiver for Direct Sequence-Spread

Spectrum System .................................................................. 24

2.2 FIR Filter Design .............................................................................. 29

2.2.1 Concepts of FIR Filter .......................................................... 29

2.2.2 Low Pass FIR Filter Design.................................................. 30

2.2.3 Distributed Arithmetic Architecture ..................................... 31

2.2.4 Simulation and Synthesis Results......................................... 31

x Contents

2.3 Discrete Cosine Transform Algorithms............................................ 32

2.3.1 Concepts of DCT .................................................................. 32

2.3.2 DCT Architectures on FPGA................................................ 33

2.3.3 Scaled 1-D 8-Point DCT Architecture.................................. 34

2.3.4 Simulation and Synthesis Results......................................... 35

2.4 Convolution Codes and Viterbi Decoding ........................................ 36

2.4.1 Concepts of Convolution Codes............................................ 36

2.4.2 Viterbi Decoder..................................................................... 38

2.4.3 Simulation and Synthesis Results......................................... 40

Appendix.................................................................................................... 42

References.................................................................................................. 46

3 ASIC Design ............................................................................................. 47

3.1 ASIC Front-End Memory Design..................................................... 47

3.1.1 Introduction........................................................................... 47

3.1.2 Memory Architecture and Specifications.............................. 48

3.1.3 Implementation and Simulations.......................................... 48

3.1.4 Results Analysis and Conclusion.......................................... 49

3.2 ASIC Front-End Matrix Multiplier Design....................................... 51

3.2.1 Introduction........................................................................... 51

3.2.2 Problem Statement................................................................ 52

3.2.3 Matrix Multiplier Design ...................................................... 52

3.2.4 Implementation and Simulations.......................................... 52

3.2.5 Analysis of Results and Conclusion ..................................... 54

3.3 Physical Design of Matrix Multiplier ............................................... 57

3.3.1 Introduction to Systolic Array Matrix Multiplier ................. 57

3.3.2 Physical Design Flow............................................................ 59

3.3.3 Results and Conclusion......................................................... 78

Appendix.................................................................................................... 79

References.................................................................................................. 81

4 Analog and Mixed Signal Design............................................................ 83

4.1 Schematic Design of OPAMP........................................................... 83

4.1.1 Introduction........................................................................... 83

4.1.2 Two Stage OPAMP Design................................................... 84

4.1.3 Results................................................................................... 93

4.2 Layout Design of OPAMP ................................................................ 93

4.2.1 Introduction........................................................................... 93

4.2.2 Layout Design....................................................................... 93

4.2.3 Summary and Results ........................................................... 98

Appendix.................................................................................................... 99

References.................................................................................................. 104

About the Author ........................................................................................... 105

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