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Vol 32 No 10 October 2011 A fastlocking alldigital delaylocked loop for phasedelay generation in an FPGAcid3 Journal of Semiconductors Chen Zhujia陈柱佳1 2 Yang Haigang杨海钢1 cid142 Liu Fei刘飞1 and Wang Yu王瑜1 2 1Institute of Electronics Chinese Academy of Sciences Beijing 100190 China 2Graduate University of the Chinese Academy of Sciences Beijing 100049 China Abstract A fastlocking alldigital delaylocked loop ADDLL is proposed for the DDR SDRAM controller interface in a field programmable gate array ......