This book is an introduction to digital system design using a modern hardware construction language,

Chisel. In this book, we focus on a higher abstraction level than usual in digital design books, to enable

you to build more complex, interacting digital systems in a shorter time.

这本书是一个使用现代硬件构建语言Chisel做数字系统设计的导论。在这本书，我们聚焦在

比平常的硬件设计更高抽象层，使搭建更为复杂和交互性的硬件系统变得可能。

This book and Chisel are targeting two groups of developers: (1) hardware designers and (2) software

programmers. Hardware designers who are fluid in VHDL or Verilog and using other languages such as

Python, Java, or Tcl to generate hardware can move to a single hardware construction language where

hardware generation is part of the language. Software programmers may become interested in hardware

design, e.g., as future chips from Intel will include programmable hardware to speed up programs. It is

perfectly fine to use Chisel as your first hardware description language.

这本书和Chisel的目标群体是两种开发者：（1）硬件设计者和（2）软件工程师。精

通VHDL或是Verilog，使用其它语言，像是Python, Java, 或是TCL/TK去生成硬件，使其变成一个

硬件建造语言，这样，生成硬件作为语言的一部分。 （2）对硬件设计有兴趣的软件程序员，

例如，像是Intel未来的芯片会添加可编程硬件用来提高程序速度。

Chisel brings advances in software engineering, such as object-orientated and functional languages,

into digital design. Chisel does not only allow to express hardware at the register-transfer level but allows

you to write hardware generators.

Chisel将诸如面向对象和函数式语言之类的软件工程的优势引入数字系统设计。 Chisel不仅

仅允许表示硬件在寄存器传输的抽象层，而且允许你编写硬件生成器。

Hardware is now commonly described with a hardware description language. The time of drawing

hardware components, even with CAD tools, is over. Some high-level schematics can give an overview of

the system but are not intended to describe the system.

硬件现在普遍通过硬件描述语言进行描述。描画硬件部分的时间，甚至是使用CAD工具画

图，这个时代已经过去了。有一些高级草图可以给你一个系统的整体描绘，但是它们不是用来

描述系统的。

The two most common hardware description languages are Verilog and VHDL. Both languages are

old, contain many legacies, and have a moving line of what constructs of the language are synthesizable

to hardware. Do not get me wrong: VHDL and Verilog are perfectly able to describe a hardware block

that can be synthesized into an ASIC. For hardware design in Chisel, Verilog serves as an intermediate

language for testing and synthesis.

两个最常用的硬件描述语言是Verilog和VHDL。 这两个语言是古老的，包括大量规则，并且

在综合到硬件的构建语言之间有一个变动的规则。 别理解错我的意思：VHDL和Verilog可以完

美描述用于综合成ASIC的硬件模块。 对于Chisel的硬件设计，verilog充当一个测试和综合的中

间语言。

This book is not a general introduction to hardware design and the fundamentals of it. For an

introduction of the basics in digital design, such as how to build a gate out of CMOS transistors, refer to

other digital design books. However, this book intends to teach digital design at an abstraction level that is

current practice to describe ASICs or designs targeting FPGA.1 As prerequisites for this book, we assume

basic knowledge of Boolean algebra and the binary number system. Furthermore, some programming

experience in any programming language is assumed. No knowledge of Verilog or VHDL is needed.

Chisel can be your first programming language to describe digital hardware. As the build process in the

examples is based on sbt and make basic knowledge of the command-line interface (CLI, also called

terminal or Unix shell) will be helpful.

这本书不是对硬件的设计和基础一般性介绍。 对有关数字设计基础知识的介绍，例如如何

使用CMOS晶体管搭建一个门电路，你要参考其它数字设计书。 但是，这本书的目的是教你在

一个抽象层中进行数字设计，作为当今描述ASIC或是设计 FPGA的例子。 2 作为这本书的前置

需求，我们假设你有一些基本的Boolean algebra和二进制数系统的知识。 更多的，一些任意编

程语言的编程经验也是需要的。不需要Verilog或是VHDL的知识。 Chisel能够成为你的第一个

编程语言用来描述数字硬件。 作为例子中的搭建过程是基于sbt和make，基本的命令行界面知

识(CLI，又称terminal或是Unix shell)会是有用的。

Chisel itself is not a big language. The basic constructs fit on one page and can be learned within

a few days. Therefore, this book is not a big book, as well. Chisel is for sure smaller than VHDL and

Verilog, which carry many legacies. The power of Chisel comes from the embedding of Chisel within

Scala, which itself in an expressive language. Chisel inherits the feature from Scala being “a language

that grows on you”Scala. However, Scala is not the topic of this book.

Chisel用来本身不是一个大的语言。基本的部分在这里one page， 可以在数日内学习。 于

是，这本书也不是一本大书。Chisel应该是比VHDL和Verilog更小, 继承很多规则。Chisel的力量

来自于它是嵌入在Scala里的，Scala本身是一个有力的语言。 Chisel继承Scala作为“a language that

grows on you’的Scala的特性 但是，Scala不是本书的话题。

This book is a tutorial in digital design and the Chisel language; it is not a Chisel language reference,

nor is it a book on complete chip design.

这本书是一个数字设计和Chisel语言的教学，不是Chisel语言的参考书籍也不是一本完整的

芯片设计书

All code examples shown in this book are extracted from complete programs that have been compiled

and tested. Therefore, the code shall not contain any syntax errors. The code examples are available

from the GitHub repository of this book. Besides showing Chisel code, we have also tried to show useful

designs and principles of good hardware description style.

所有的书中代码例子来自经过编译和测试过的程序。所以，代码不应该含有任何语法问题。

代码例子在本书的github repo里。除了提供Chisel代码以外，我也试图提供有用的设计和好的硬

件描述风格的规则。

所有的书中代码例子来自经过编译和测试过的程序。所以，代码不应该含有任何语法问题。

代码例子在本书的GitHub 仓库里。除了提供Chisel代码以外，我也试图提供有用的设计和好的

硬件描述风格的规则。

This book is optimized for reading on a laptop or tablet (e.g., an iPad). We include links to further

reading in the running text, mostly to Wikipedia articles.

这本书在笔电或是平板上为阅读经过了优化。我们在字里行间提供了链接，大多数

是Wikipedia的文章。