时钟倍频后,通过Modelsim仿真验证任意占空比可调的PWM信号sim\\glbl.v
...\\pwm_div.cr.mti
...\\pwm_div.mpf
...\\pwm_div.v
...\\pwm_div.v.bak
...\\rom16.mif
...\\rom16.v
...\\tb.v
...\\transcript
...\\vsim.wlf
...\\wave.do
...\\.ork\\@p@w@m_div\\verilog.asm
...\\....\\..........\\verilog.rw
...\\....\\..........\\_primary.dat
...\\....\\..........\\_primary.dbs
...\\....\\..........\\_primary.vhd
...\\....\\glbl\\verilog.asm
...\\....\\....\\verilog.rw
...\\....\\....\\_primary.dat
...\\....\\....\\_primary.dbs
...\\....\\....\\_primary.vhd
...\\....\\rom16\\verilog.asm
...\\....\\.....\\verilog.rw
...\\....\\.....\\_primary.dat
...\\....\\.....\\_primary.dbs
...\\....\\.....\\_primary.vhd
...\\....\\tb\\verilog.asm
...\\....\\..\\verilog.rw
...\\....\\..\\_primary.dat
...\\....\\..\\_primary.dbs
...\\....\\..\\_primary.vhd
...\\....\\_info
...\\....\\_vmake
...\\....\\@p@w@m_div
...\\....\\glbl
...\\....\\rom16
...\\....\\tb
...\\....\\_temp
...\\work
sim