2020年04月02日 | msp430f5438定时器1s的程序

void time_init_1s()

{

  TA1CCTL0 = CCIE;                          // CCR0 interrupt enabled

  TA1CCR0 = 16383;

  TA1CTL = TASSEL_1 + MC_1 + TACLR;         // ACLK, Up to CCR0 , clear TAR 

}

//中断服务程序

#pragma vector=TIMER1_A0_VECTOR

__interrupt void TIMER1_A0_ISR(void)

{

  P5OUT ^=BIT4; 

  TA1CCR0 += 16383;                         // Add Offset to CCR0

}

时钟设置：

void clk_init()

{

  //ACLK = REFO = 32kHz, MCLK = SMCLK = 25MHz

   WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT

  UCSCTL3 |= SELREF_2;                      // Set DCO FLL reference = REFO

  UCSCTL4 |= SELA_2;                        // Set ACLK = REFO

  __bis_SR_register(SCG0);                  // Disable the FLL control loop

  UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx

  UCSCTL1 = DCORSEL_7;                      // Select DCO range 25MHz operation

  UCSCTL2 = FLLD_1 +762;                   // Set DCO Multiplier for 25MHz

                                            // (N + 1) * FLLRef = Fdco

                                            // (762 + 1) * 32768 = 25MHz

                                            // Set FLL Div = fDCOCLK/2

  __bic_SR_register(SCG0);                  // Enable the FLL control loop

  // Worst-case settling time for the DCO when the DCO range bits have been

  // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx

  // UG for optimization.

  // 32 x 32 x 25 MHz / 32,768 Hz = 782000 = MCLK cycles for DCO to settle

  __delay_cycles(782000);

  // Loop until XT1,XT2 & DCO fault flag is cleared

  do

  {

    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);

                                            // Clear XT2,XT1,DCO fault flags

    SFRIFG1 &= ~OFIFG;                      // Clear fault flags

  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag              

}

msp430f有两个中断向量，还是一Ti的一个例程来说吧

//******************************************************************************

//  MSP430F5438 Demo - Timer_A3, Toggle P1.0;P2.1-3, Cont. Mode ISR, 32kHz ACLK

//

//  Description: Use Timer1_A CCRx units and overflow to generate four

//  independent timing intervals. For demonstration, CCR0, CCR1 and CCR2

//  output units are optionally selected with port pins P2.1, P2.2 and P2.3

//  in toggle mode. As such, these pins will toggle when respective CCRx

//  registers match the TAR counter. Interrupts are also enabled with all

//  CCRx units, software loads offset to next interval only - as long as

//  the interval offset is added to CCRx, toggle rate is generated in

//  hardware. Timer1_A overflow ISR is used to toggle P1.0 with software.

//  Proper use of the TAIV interrupt vector generator is demonstrated.

//  ACLK = TACLK = 32kHz, MCLK = SMCLK = default DCO ~1.045MHz

//

//  As coded and with TACLK = 32768Hz, toggle rates are:

//  P2.1= CCR0 = 32768/(2*4) = 4096Hz

//  P2.2= CCR1 = 32768/(2*16) = 1024Hz

//  P2.3= CCR2 = 32768/(2*100) = 163.84Hz

//  P1.0= overflow = 32768/(2*65536) = 0.25Hz

//

//               MSP430F5438

//            -------------------

//        /||                   |

//         | |                   |

//         --|RST                |

//           |                   |

//           |         P2.1/TA1.0|--> CCR0

//           |         P2.2/TA1.1|--> CCR1

//           |         P2.3/TA1.2|--> CCR2

//           |               P1.0|--> Overflow/software

//           |               P1.0|--> LED

//

//   M Smertneck / W. Goh

//   Texas Instruments Inc.

//   September 2008

//   Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B

//******************************************************************************

#include "msp430x54x.h"

void main(void)

{

  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT

  P2SEL |= 0x0E;                            // P1.1 - P1.3 option select

  P2DIR |= 0x0E;                            // P2.1 - P2.3 outputs

  P1DIR |= 0x01;                            // P1.0 - Outputs

  TA1CCTL0 = OUTMOD_4 + CCIE;               // CCR0 toggle, interrupt enabled

  TA1CCTL1 = OUTMOD_4 + CCIE;               // CCR1 toggle, interrupt enabled

  TA1CCTL2 = OUTMOD_4 + CCIE;               // CCR2 toggle, interrupt enabled

  TA1CTL = TASSEL_1 + MC_2 + TACLR + TAIE;  // ACLK, contmode, clear TAR,

                                            // interrupt enabled

  __bis_SR_register(LPM3_bits + GIE);       // Enter LPM3, interrupts enabled

  __no_operation();                         // For debugger

}

// Timer1 A0 interrupt service routine

#pragma vector=TIMER1_A0_VECTOR

__interrupt void Timer_A0 (void)

{

  TA1CCR0 += 4;                             // Add Offset to CCR0

}

// Timer_A3 Interrupt Vector (TAIV) handler

#pragma vector=TIMER1_A1_VECTOR

__interrupt void TIMER1_A1_ISR(void)

{

  switch(__even_in_range(TA1IV,14))

  {

    case 0: break;                  

    case 2:  TA1CCR1 += 16;                 // Add Offset to CCR1

             break;

    case 4:  TA1CCR2 += 100;                // Add Offset to CCR2

             break;

    case 6:  break;                         // CCR3 not used

    case 8:  break;                         // CCR4 not used

    case 10: break;                         // CCR5 not used

    case 12: break;                         // Reserved not used

    case 14: P1OUT ^= 0x01;                 // overflow

             break;

    default: break;

 }

}

从datasheet可以看出模式4的波形。

看了两天时钟，定时器，想在写点体会，方法也难，最后还是建议大家多看datasheet，看英文的比较好，中文的太垃圾了