2021年10月08日 | STM8S CPU主时钟

STM8S上电后的时钟来源:

/* Public functions ----------------------------------------------------------*/
/**
* @addtogroup CLK_Public_Functions
* @{
*/

/**
* @brief Deinitializes the CLK peripheral registers to their default reset
* values.
* @param None
* @retval None
* @par Warning:
* Resetting the CCOR register: n
* When the CCOEN bit is set, the reset of the CCOR register require
* two consecutive write instructions in order to reset first the CCOEN bit
* and the second one is to reset the CCOSEL bits.
*/
void CLK_DeInit(void)
{
CLK->ICKR = CLK_ICKR_RESET_VALUE;
CLK->ECKR = CLK_ECKR_RESET_VALUE;
CLK->SWR = CLK_SWR_RESET_VALUE; // 0xE1
CLK->SWCR = CLK_SWCR_RESET_VALUE;
CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE;
CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE;
CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE;
CLK->CSSR = CLK_CSSR_RESET_VALUE;
CLK->CCOR = CLK_CCOR_RESET_VALUE;
while ((CLK->CCOR & CLK_CCOR_CCOEN)!= 0)
{}
CLK->CCOR = CLK_CCOR_RESET_VALUE;
CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE;
CLK->SWIMCCR = CLK_SWIMCCR_RESET_VALUE;
}

CPU上电后是内站HSI时钟，16MHz :   16 MHz high-speed internal RC oscillator (HSI)

得到其它的时钟，可以通过时钟分频寄存器(CLK_CKDIVR)对时钟进行分频:

CPU 时钟分频器
CPU时钟(f CPU )由主时钟(f MASTER )分频而来，分频因子由时钟分频寄存器(CLK_CKDIVR)中的位
CPUDIV[2:0]决定。共7个分频因子可供选择(1至128中，2的幂)。f CPU 为CPU和窗口看门狗提供时钟。

那么CPU主时钟来源:

4.5 Clock controller
The clock controller distributes the system clock (fMASTER) coming from different
oscillators to the core and the peripherals. It also manages clock gating for low power
modes and ensures clock robustness.
Features
 Clock prescaler: to get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
 Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
 Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
 Master clock sources: four different clock sources can be used to drive the master
clock:
– 1-16 MHz high-speed external crystal (HSE)
– Up to 16 MHz high-speed user-external clock (HSE user-ext)
– 16 MHz high-speed internal RC oscillator (HSI)
– 128 kHz low-speed internal RC (LSI)
 Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz
clock (HSI/8). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
 Clock security system (CSS): This feature can be enabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS
and an interrupt can optionally be generated.
 Configurable main clock output (CCO): This outputs an external clock for use by the
application.