《基于“矿板”低成本学习FPGA》移植OpenC906第二篇-约束综合实现生成bit文件与IO扩展板设计

EmbeddedLee

2024-08-31

阅读数：

一. 前言

前面我们完成了 C906 的工程创建和综合，现在开始就可以进行引脚和时钟约束进行实现生成 bit 文件了。同时我们根据板子插座和需要的引脚设计一个简单的 IO 扩展板，方便调试。

二. 约束

2.1 引脚约束

根据顶层文件可以看到需要以下 18 个引脚

其中 clk 是时钟输入

j 开头的是 6 个 jtag 相关引脚， jclk 是 jtag 的时钟输入。其中 jrst_b 是对调试接口复位， jnrst_b 是对目标系统复位。

一个串口 2 个引脚 uart0_sout,uart0_sin

一个 8p 的 IO ,b_pad_gpio_porta

一个系统复位 rst_b

clk 先直接使用外部晶振，先跑 50MHz ，后面再尝试使用内部时钟资源倍频跑更高的速率。

clk 和 jclk 都要做时钟约束。

module c906_top(    clk,    rst_b,    uart0_sin,    uart0_sout,    b_pad_gpio_porta,    jclk,    jrst_b,    jnrst_b,    jtg_tdi,    jtg_tdo,    jtg_tms );    input clk;    inout[7:0] b_pad_gpio_porta;    input rst_b;    input jclk;    input jtg_tdi;    input jtg_tms ;      input uart0_sin;    output jtg_tdo;    output uart0_sout;    input jnrst_b;    input jrst_b;        soc x_soc(  .i_pad_clk           ( clk                  ),  .b_pad_gpio_porta    ( b_pad_gpio_porta     ),  .i_pad_jtg_trst_b    ( jrst_b               ),  .i_pad_jtg_nrst_b    ( jnrst_b                ),  .i_pad_jtg_tclk      ( jclk                 ),  .i_pad_jtg_tdi       ( jtg_tdi              ),  .i_pad_jtg_tms       ( jtg_tms              ),  .i_pad_uart0_sin     ( uart0_sin            ),  .o_pad_jtg_tdo       ( jtg_tdo              ),  .o_pad_uart0_sout    ( uart0_sout           ),  .i_pad_rst_b         ( rst_b                ));endmodule

打开约束向导

左侧 Flow 导航选中 SYNTHSIS ，菜单栏 Window->I/O ports 显示对应界面

我们对应 JK1 插座的如下引脚

对应我们设计的 IO 扩展板的如下位置

配置如下

Ctrl+s 保存

2.2 时钟约束

打开 SYNTHSIS 下的约束向导

CLK 为 50M ， JCLK 为 jtag 仿真器输出 soc 输入，先按照 1M 设计，如果不行以后再降低 ( 最低 100KHz)

所有子时钟分批都设置为 1

输入延迟先不设置

输出延迟也不设置

最终约束文件 xdc 内容如下

set_property DRIVE 12 [get_ports {b_pad_gpio_porta[7]}]set_property PACKAGE_PIN E29 [get_ports {b_pad_gpio_porta[7]}]set_property PACKAGE_PIN A25 [get_ports {b_pad_gpio_porta[6]}]set_property PACKAGE_PIN H25 [get_ports {b_pad_gpio_porta[5]}]set_property PACKAGE_PIN E24 [get_ports {b_pad_gpio_porta[4]}]set_property PACKAGE_PIN E25 [get_ports {b_pad_gpio_porta[3]}]set_property PACKAGE_PIN H24 [get_ports {b_pad_gpio_porta[2]}]set_property PACKAGE_PIN A26 [get_ports {b_pad_gpio_porta[1]}]set_property PACKAGE_PIN F25 [get_ports {b_pad_gpio_porta[0]}]set_property IOSTANDARD LVCMOS18 [get_ports {b_pad_gpio_porta[7]}]set_property IOSTANDARD LVCMOS18 [get_ports {b_pad_gpio_porta[6]}]set_property IOSTANDARD LVCMOS18 [get_ports {b_pad_gpio_porta[5]}]set_property IOSTANDARD LVCMOS18 [get_ports {b_pad_gpio_porta[4]}]set_property IOSTANDARD LVCMOS18 [get_ports {b_pad_gpio_porta[3]}]set_property IOSTANDARD LVCMOS18 [get_ports {b_pad_gpio_porta[2]}]set_property IOSTANDARD LVCMOS18 [get_ports {b_pad_gpio_porta[1]}]set_property IOSTANDARD LVCMOS18 [get_ports {b_pad_gpio_porta[0]}]set_property PULLTYPE PULLUP [get_ports {b_pad_gpio_porta[7]}]set_property PULLTYPE PULLUP [get_ports {b_pad_gpio_porta[6]}]set_property PULLTYPE PULLUP [get_ports {b_pad_gpio_porta[5]}]set_property PULLTYPE PULLUP [get_ports {b_pad_gpio_porta[4]}]set_property PULLTYPE PULLUP [get_ports {b_pad_gpio_porta[3]}]set_property PULLTYPE PULLUP [get_ports {b_pad_gpio_porta[2]}]set_property PULLTYPE PULLUP [get_ports {b_pad_gpio_porta[1]}]set_property PULLTYPE PULLUP [get_ports {b_pad_gpio_porta[0]}]set_property PACKAGE_PIN D27 [get_ports clk]set_property IOSTANDARD LVCMOS18 [get_ports clk]set_property IOSTANDARD LVCMOS18 [get_ports jclk]set_property IOSTANDARD LVCMOS18 [get_ports jnrst_b]set_property IOSTANDARD LVCMOS18 [get_ports jrst_b]set_property IOSTANDARD LVCMOS18 [get_ports jtg_tdi]set_property IOSTANDARD LVCMOS18 [get_ports jtg_tdo]set_property IOSTANDARD LVCMOS18 [get_ports jtg_tms]set_property IOSTANDARD LVCMOS18 [get_ports rst_b]set_property IOSTANDARD LVCMOS18 [get_ports uart0_sin]set_property IOSTANDARD LVCMOS18 [get_ports uart0_sout]set_property PULLTYPE PULLUP [get_ports clk]set_property PULLTYPE PULLUP [get_ports jclk]set_property PULLTYPE PULLUP [get_ports jnrst_b]set_property PULLTYPE PULLUP [get_ports jrst_b]set_property PULLTYPE PULLUP [get_ports jtg_tdi]set_property PULLTYPE PULLUP [get_ports jtg_tdo]set_property PULLTYPE PULLUP [get_ports jtg_tms]set_property PULLTYPE PULLUP [get_ports rst_b]set_property PULLTYPE PULLUP [get_ports uart0_sin]set_property PULLTYPE PULLUP [get_ports uart0_sout]set_property PACKAGE_PIN A27 [get_ports jclk]set_property PACKAGE_PIN C25 [get_ports jnrst_b]set_property PACKAGE_PIN H30 [get_ports jrst_b]set_property PACKAGE_PIN C29 [get_ports jtg_tdi]set_property PACKAGE_PIN B29 [get_ports jtg_tdo]set_property PACKAGE_PIN B27 [get_ports jtg_tms]set_property PACKAGE_PIN H20 [get_ports rst_b]set_property PACKAGE_PIN A23 [get_ports uart0_sin]set_property PACKAGE_PIN B23 [get_ports uart0_sout]set_property SLEW SLOW [get_ports {b_pad_gpio_porta[7]}]set_property SLEW SLOW [get_ports {b_pad_gpio_porta[6]}]set_property SLEW SLOW [get_ports {b_pad_gpio_porta[5]}]set_property SLEW SLOW [get_ports {b_pad_gpio_porta[4]}]set_property SLEW SLOW [get_ports {b_pad_gpio_porta[3]}]set_property SLEW SLOW [get_ports {b_pad_gpio_porta[2]}]set_property SLEW SLOW [get_ports {b_pad_gpio_porta[1]}]set_property SLEW SLOW [get_ports {b_pad_gpio_porta[0]}]create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk]create_clock -period 1000.000 -name jclk -waveform {0.000 500.000} [get_ports jclk]set_property ASYNC_REG true [get_cells {x_soc/x_cpu_sub_system_axi/x_c906_wrapper/x_c906_dtm_top/x_tdt_dmi/x_tdt_apb_master/x_tdt_dmi_pulse_sync_1/x_tdt_dmi_sync_dff/sync_ff_reg[0]}]set_property ASYNC_REG true [get_cells {x_soc/x_cpu_sub_system_axi/x_c906_wrapper/x_c906_dtm_top/x_tdt_dmi/x_tdt_apb_master/x_tdt_dmi_pulse_sync_1/x_tdt_dmi_sync_dff/sync_ff_reg[1]}]set_property ASYNC_REG true [get_cells {x_soc/x_cpu_sub_system_axi/x_c906_wrapper/x_c906_dtm_top/x_tdt_dmi/x_tdt_apb_master/x_tdt_dmi_pulse_cmd_vld/x_tdt_dmi_sync_dff_back/sync_ff_reg[0]}]set_property ASYNC_REG true [get_cells {x_soc/x_cpu_sub_system_axi/x_c906_wrapper/x_c906_dtm_top/x_tdt_dmi/x_tdt_apb_master/x_tdt_dmi_pulse_cmd_vld/x_tdt_dmi_sync_dff_back/sync_ff_reg[1]}]set_property ASYNC_REG true [get_cells {x_soc/x_cpu_sub_system_axi/x_c906_wrapper/x_c906_dtm_top/x_tdt_dmi/x_tdt_apb_master/x_tdt_dmi_pulse_dmihardreset/x_tdt_dmi_sync_dff_back/sync_ff_reg[0]}]set_property ASYNC_REG true [get_cells {x_soc/x_cpu_sub_system_axi/x_c906_wrapper/x_c906_dtm_top/x_tdt_dmi/x_tdt_apb_master/x_tdt_dmi_pulse_dmihardreset/x_tdt_dmi_sync_dff_back/sync_ff_reg[1]}]set_property ASYNC_REG true [get_cells {x_soc/x_cpu_sub_system_axi/x_c906_wrapper/x_c906_dtm_top/x_tdt_dmi/x_tdt_apb_master/x_tdt_dmi_pulse_sync_1/x_tdt_dmi_sync_dff_back/sync_ff_reg[0]}]set_property ASYNC_REG true [get_cells {x_soc/x_cpu_sub_system_axi/x_c906_wrapper/x_c906_dtm_top/x_tdt_dmi/x_tdt_apb_master/x_tdt_dmi_pulse_sync_1/x_tdt_dmi_sync_dff_back/sync_ff_reg[1]}]set_property ASYNC_REG true [get_cells {x_soc/x_cpu_sub_system_axi/x_c906_wrapper/x_c906_dtm_top/x_tdt_dmi/x_tdt_apb_master/x_tdt_dmi_pulse_dmihardreset/x_tdt_dmi_sync_dff/sync_ff_reg[0]}]set_property ASYNC_REG true [get_cells {x_soc/x_cpu_sub_system_axi/x_c906_wrapper/x_c906_dtm_top/x_tdt_dmi/x_tdt_apb_master/x_tdt_dmi_pulse_dmihardreset/x_tdt_dmi_sync_dff/sync_ff_reg[1]}]set_property ASYNC_REG true [get_cells {x_soc/x_cpu_sub_system_axi/x_c906_wrapper/x_c906_dtm_top/x_tdt_dmi/x_tdt_apb_master/x_tdt_dmi_pulse_cmd_vld/x_tdt_dmi_sync_dff/sync_ff_reg[0]}]set_property ASYNC_REG true [get_cells {x_soc/x_cpu_sub_system_axi/x_c906_wrapper/x_c906_dtm_top/x_tdt_dmi/x_tdt_apb_master/x_tdt_dmi_pulse_cmd_vld/x_tdt_dmi_sync_dff/sync_ff_reg[1]}]set_property OFFCHIP_TERM NONE [get_ports jtg_tdo]set_property OFFCHIP_TERM NONE [get_ports uart0_sout]set_property OFFCHIP_TERM NONE [get_ports b_pad_gpio_porta[7]]set_property OFFCHIP_TERM NONE [get_ports b_pad_gpio_porta[6]]set_property OFFCHIP_TERM NONE [get_ports b_pad_gpio_porta[5]]set_property OFFCHIP_TERM NONE [get_ports b_pad_gpio_porta[4]]set_property OFFCHIP_TERM NONE [get_ports b_pad_gpio_porta[3]]set_property OFFCHIP_TERM NONE [get_ports b_pad_gpio_porta[2]]set_property OFFCHIP_TERM NONE [get_ports b_pad_gpio_porta[1]]set_property OFFCHIP_TERM NONE [get_ports b_pad_gpio_porta[0]]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[12]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[12]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[13]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[13]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[14]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[14]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[15]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[15]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[16]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[16]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[17]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[17]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[18]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[18]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[19]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[19]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[20]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[20]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[21]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[21]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[22]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[22]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[23]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[23]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[24]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[24]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[25]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[25]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[26]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[26]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[27]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[27]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[28]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[28]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[29]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[29]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[30]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[30]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[31]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[31]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[32]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[32]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[33]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[33]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[34]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[34]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[35]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[35]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[36]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[36]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[37]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[37]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[38]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[38]/Q}]create_generated_clock -name {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg_n_0_[39]} -source [get_ports clk] -divide_by 1 [get_pins {x_soc/x_apb/x_apb_bridge/apb_xx_paddr_reg[39]/Q}]create_generated_clock -name x_soc/x_apb/x_apb_bridge/apb_xx_psel -source [get_ports clk] -divide_by 1 [get_pins x_soc/x_apb/x_apb_bridge/apb_xx_psel_reg/Q]create_generated_clock -name x_soc/x_apb/x_apb_bridge/apb_xx_pwrite -source [get_ports clk] -divide_by 1 [get_pins x_soc/x_apb/x_apb_bridge/apb_xx_pwrite_reg/Q]create_generated_clock -name x_soc/x_cpu_sub_system_axi/x_c906_wrapper/sys_apb_clk_reg_0 -source [get_ports clk] -divide_by 1 [get_pins x_soc/x_cpu_sub_system_axi/x_c906_wrapper/sys_apb_clk_reg/Q]set_clock_groups -asynchronous -group [get_clocks x_soc/x_cpu_sub_system_axi/x_c906_wrapper/sys_apb_clk_reg_0] -group [get_clocks jclk]set_clock_groups -asynchronous -group [get_clocks jclk] -group [get_clocks x_soc/x_cpu_sub_system_axi/x_c906_wrapper/sys_apb_clk_reg_0]