parameter idle=00,
jia=01,
cheng=11,
yuan=10;
always@(posedge clk)
if(!rst)
begin
j<=0;
c<=0;
y<=0;
state<=idle;
end
else begin
case(state)
idle:if(en)begin
state<=cheng;
flog<=0;
c<=1;j<=0;y<=0;
end
cheng: begin if(en) begin
if(!flog) begin state<=jia;
c<=0;j<=1;y<=0;
end
else begin state<=yuan;
c<=0;j<=0;y<=1;
end
flog<=flog+1;
end
else begin
state<=idle;
c<=0;j<=0;y<=0;
end
end
jia:begin
if(flog) begin state<=jia;
c<=0;j<=1;y<=0;
end
else begin state<=cheng;
c<=1;j<=0;y<=0;
end
flog<=flog+1;
end
yuan:begin
if(!flog) begin state<=yuan;
c<=0;j<=0;y<=0;
end
else begin state<=cheng;
c<=1;j<=0;y<=0;
end
flog<=flog+1;
end
endcase
end