[资料分享] ADI Parallel Port SDRAM Controller Reference Design

Introduction The ADI parallel port SDRAM controller reference design connects SDRAM to the parallel port of an Analog Devices Incorporated (ADI)
ADSP-2126x Sharc DSP device and is implemented in Altera® FPGAs and CPLDs.
Altera supplies the reference design as Verilog HDL source code. The reference design includes a testbench that allows you to test the Verilog HDL source code.
The purpose of this reference design is to demonstrate that Altera devices provide a low cost SDRAM interface for ADI Sharc DSP devices.