[讨论] 代码出错，高手帮忙看看

lx773533 2010-5-10 21:51 楼主

--8位10进制频率计
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ftctrl3 is
  port(clkk:in std_logic;
   cnt_en:out std_logic;
   rst_cnt:out std_logic;
      load:out std_logic);
end ftctrl3;
architecture one of ftctrl3 is
signal clk1:std_logic;
begin
  process(clkk)
  variable cqi:std_logic_vector(3 downto 0);
  variable cq2:std_logic_vector(6 downto 0);
  begin
if clkk'event and clkk='1' then
if cq2<125 then cq2:=cq2+1;
   else cq2:=(others=>'0');end if;
if cq2=124 then clk1<='1';
   else clk1<='0'; end if;

  if clk1'event and clk1='1' then
  if cqi<15 then cqi:=cqi+1;
   else cqi:=(others=>'0');end if;
  if cqi<8 then cnt_en<='1';
  else cnt_en<='0';  end if;
  if cqi=11 then load<='1';
  else load<='0';  end if;
  if cqi=14 then rst_cnt<='1';
  else rst_cnt<='0';end if;
  end if;
  end if;
end process;
end one;
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
Info: Processing started: Mon May 10 21:49:15 2010
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lx -c lx
Warning: Ignored assignments for entity "ftctrl3" -- entity does not exist in design
Warning: Assignment of entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top is ignored
Warning: Assignment of entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top is ignored
Warning: Assignment of entity set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top is ignored
Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -section_id Top is ignored
Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id Top is ignored
Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id Top is ignored
Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -section_id Top is ignored
Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -section_id Top is ignored
Warning: Assignment of entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -section_id Top is ignored
Warning: Ignored assignments for entity "lx" -- entity does not exist in design
Warning: Assignment of entity set_global_assignment -name LL_ROOT_REGION ON -entity lx -section_id "Root Region" is ignored
Warning: Assignment of entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity lx -section_id "Root Region" is ignored
Info: Found 2 design units, including 1 entities, in source file ftctrl3.vhd
Info: Found design unit 1: ftctrl3-one
Info: Found entity 1: ftctrl3
Info: Found 2 design units, including 1 entities, in source file ../../../experiment/8位10进制频率计的设计/FTCTRL2.vhd
Info: Found design unit 1: FTCTRL2-ONE
Info: Found entity 1: FTCTRL2
Info: Found 2 design units, including 1 entities, in source file Vhdl3.vhd
Info: Found design unit 1: vhdl3-one
Info: Found entity 1: vhdl3
Info: Elaborating entity "ftctrl3" for the top level hierarchy
Error (10821): HDL error at ftctrl3.vhd(20): can't infer register for "rst_cnt" because its behavior does not match any supported register model
Info (10041): Inferred latch for "rst_cnt" at ftctrl3.vhd(16)
Error (10821): HDL error at ftctrl3.vhd(20): can't infer register for "load" because its behavior does not match any supported register model
Info (10041): Inferred latch for "load" at ftctrl3.vhd(16)
Error (10821): HDL error at ftctrl3.vhd(20): can't infer register for "cnt_en" because its behavior does not match any supported register model
Info (10041): Inferred latch for "cnt_en" at ftctrl3.vhd(16)
Error (10821): HDL error at ftctrl3.vhd(20): can't infer register for "cqi[0]" because its behavior does not match any supported register model
Info (10041): Inferred latch for "cqi[0]" at ftctrl3.vhd(20)
Error (10821): HDL error at ftctrl3.vhd(20): can't infer register for "cqi[1]" because its behavior does not match any supported register model
Info (10041): Inferred latch for "cqi[1]" at ftctrl3.vhd(20)
Error (10821): HDL error at ftctrl3.vhd(20): can't infer register for "cqi[2]" because its behavior does not match any supported register model
Info (10041): Inferred latch for "cqi[2]" at ftctrl3.vhd(20)
Error (10821): HDL error at ftctrl3.vhd(20): can't infer register for "cqi[3]" because its behavior does not match any supported register model
Info (10041): Inferred latch for "cqi[3]" at ftctrl3.vhd(20)
Error (10822): HDL error at ftctrl3.vhd(20): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at ftctrl3.vhd(26): couldn't implement registers for assignments on this clock edge
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 10 errors, 13 warnings
Error: Peak virtual memory: 170 megabytes
Error: Processing ended: Mon May 10 21:49:18 2010
Error: Elapsed time: 00:00:03
Error: Total CPU time (on all processors): 00:00:03
Error: Quartus II Full Compilation was unsuccessful. 12 errors, 13 warnings
这是什么错误啊？求。。。解。。。