[讨论] 关于VGA显示扫描模块

用vga640480这程序  实现一个HS里包含800个CLK  1个VS里包含525个HS
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vga640480 is
  port (clk :in std_logic;
       hs,vs,r,g,b :out std_logic;
       rgbin :in std_logic_vector(2 downto 0);
       hcntout,vcntout :out std_logic_vector(9 downto 0));
end vga640480;
architecture one of vga640480 is
signal hcnt,vcnt :std_logic_vector(9 downto 0);
begin
hcntout <= hcnt; vcntout<=vcnt;
process(clk) begin
if (rising_edge(clk))then
  if(hcnt<800)then hcnt<=hcnt+1;
else hcnt<=(others=> '0' );end if;
end if;
end process;
process(clk) begin
if(rising_edge(clk))then
  if(hcnt=640+8)then
if(vcnt<800*525)then vcnt<=vcnt+1;
else vcnt<=(others=>'0');end if;
end if;
end if;
end process;
process(clk) begin
if(rising_edge(clk))then
if((hcnt=640+8+8)and(hcnt<640+8+96))then hs<='0';
else hs<='1';end if;
end if;
end process;
process(vcnt) begin
if(hcnt>=(480+8+2)*800)and(hcnt<(480+8+2+2)*800)then vs<='0';
else vs<='1';end if;
end process;
process(clk) begin
if(rising_edge(clk))then
if(hcnt<640 and vcnt<480) then
r<=rgbin(2);g<=rgbin(1);b<=rgbin(0);
else r<='0';g<='0';b<='0';end if;
end if;
end process;
end one;           谁能帮下怎么改程序才能得出正确的波形，这个是我改了次的，波形还是不对

几个if语句里的计数器比较值有问题

1、“if (vcnt < 800*525) then”
　　vcnt只有10位，哪来这么大的值？

2、“if (hcnt >= (480+8+2)*800) and (hcnt < (480+8+2+2)*800) then”
　　hcnt也只有10位，同上问题。

建议用严谨的书写格式，增强程序的可读性。

下面的代码没改正错误，仅调整了书写格式：
----------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity vga640480 is
  port (clk :in std_logic;
       hs,vs,r,g,b :out std_logic;
       rgbin :in std_logic_vector(2 downto 0);
       hcntout,vcntout :out std_logic_vector(9 downto 0));
end vga640480;

architecture one of vga640480 is

  signal hcnt,vcnt :std_logic_vector(9 downto 0);

  begin

  hcntout <= hcnt;
  vcntout <= vcnt;

  process(clk)
  begin
    if (rising_edge(clk)) then
      if (hcnt < 800) then
        hcnt <= hcnt + 1;
      else
        hcnt <= (others=> '0' );
      end if;
    end if;
  end process;

  process(clk)
  begin
    if (rising_edge(clk)) then
      if (hcnt = 640+8) then
        if (vcnt < 800*525) then
          vcnt <= vcnt + 1;
        else
          vcnt <= (others => '0');
        end if;
      end if;
    end if;
  end process;

  process(clk)
  begin
    if (rising_edge(clk)) then
      if ((hcnt = 640+8+8) and (hcnt < 640+8+96)) then
        hs <= '0';
      else
        hs <= '1';
      end if;
    end if;
  end process;

  process(vcnt)
  begin
    if (hcnt >= (480+8+2)*800) and (hcnt < (480+8+2+2)*800) then
      vs <= '0';
    else
      vs <= '1';
    end if;
  end process;

  process(clk)
  begin
    if (rising_edge(clk)) then
      if ((hcnt < 640) and (vcnt < 480)) then
        r <= rgbin(2);
        g <= rgbin(1);
        b <= rgbin(0);
      else
        r <= '0';
        g <= '0';
        b <= '0';
      end if;
    end if;
  end process;

end one;

没改前的程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vga640480 is
  port (clk :in std_logic;
       hs,vs,r,g,b :out std_logic;
       rgbin :in std_logic_vector(2 downto 0);
       hcntout,vcntout :out std_logic_vector(9 downto 0));
end vga640480;
architecture one of vga640480 is
signal hcnt,vcnt :std_logic_vector(9 downto 0);
begin
hcntout <= hcnt; vcntout<=vcnt;
process(clk) begin
if (rising_edge(clk))then
if(hcnt<800)then hcnt<=hcnt+1;
else hcnt<=(others=> '0' );end if;
end if;
end process;
process(clk) begin
if(rising_edge(clk))then
  if(hcnt=640+8)then
if(vcnt<525)then vcnt<=vcnt+1;
else vcnt<=(others=>'0');end if;
end if;
end if;
end process;
process(clk) begin
if(rising_edge(clk))then
if((hcnt=640+8+8)and(hcnt<640+8+96))then hs<='0';
else hs<='1';end if;
end if;
end process;
process(vcnt) begin
if((hcnt>=480+8+2)and(hcnt<480+8+2+2))then vs<='0';
else vs<='1';end if;
end process;
process(clk) begin
if(rising_edge(clk))then
if(hcnt<640 and vcnt<480) then
r<=rgbin(2);g<=rgbin(1);b<=rgbin(0);
else r<='0';g<='0';b<='0';end if;
end if;
end process;
end one;    这个是我没改前的程序

错误：“if ((hcnt = 640+8+8) and (hcnt < 640+8+96)) then”

显然是 (hcnt = 640+8+8) 漏掉一个 > 号，使得水平同步脉宽只有一个时钟，太窄了。

回复 楼主 litei0000 的帖子

这个有用，自己看看哦···
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vga640480 is
port(clk:in std_logic;
     hs,vs,r,g,b:out std_logic;
     rgbin:in std_logic_vector(2 downto 0);
     hcntout,vcntout:out std_logic_vector(9 downto 0));
end vga640480;
architecture one of vga640480 is
signal hcnt,vcnt:std_logic_vector(9 downto 0);
begin
hcntout<=hcnt;
vcntout<=vcnt;
process(clk) begin
if(rising_edge(clk))then
   if(hcnt<800) then hcnt<=hcnt+1;
   else hcnt<=(others=>'0');
   end if;
end if;
end process;
process(clk)begin
if(rising_edge(clk))then
   if(hcnt=640+8) then
    if(vcnt<525) then vcnt<=vcnt+1;
     else vcnt<=(others=>'0');
    end if;
   end if;
end if;
end process;
process(clk)begin
  if(rising_edge(clk)) then
    if(hcnt>=640+8+8)and(hcnt<640+8+8+96)then
    hs<='0';
    else hs<='1';
    end if;
  end if;
end process;
process(clk)begin
if(rising_edge(clk))then
  if(hcnt<640 and vcnt<480) then
    r<=rgbin(2);
    g<=rgbin(1);
    b<=rgbin(0);
  else r<='0';
       g<='0';
       b<='0';
  end if;
end if;
end process;
end one;

楼主做出来了不？若做出来了能否把你定制ROM的那一块发来看看，主要是.MIF或者.HEX文件那一部分，谢谢！