[讨论] LMX2592的寄存器控制

yangyang_l 2019-3-19 09:54 楼主

我用TI的LMX2592芯片产生5G的时钟信号，用FPGA对其寄存器进行控制，使用的是SPI的方式。硬件是自己设计的，测量了芯片的供电在指定的范围内。但就是读不出寄存器里的数据。SPI的控制时序如下图，想要实现的是读出寄存器中的数据。 FPGA中的程序是先给LMX2592写入24'b0000_0000_0000_0000_0000_0010，resetLMX2592，等待1us后将LMX2592设置为readback的模式，写入的数据为24'b0000_0000_0010_0011_0001_1000.之后就是读取寄存器中的数据，但无法读出数据。请问有人用过LMX2592这个芯片没？请指教一下呀~~

回复评论（4）

沙发 ylyfxzsx

请关注TI社区，这里有相同的问题，配置寄存器时每个寄存器之间的时间间隔需要长一些。https://e2echina.ti.com/question ... locks/f/59/t/129490

点赞 2019-3-27 22:42

板凳 yangyang_l

引用: ylyfxzsx 发表于 2019-3-27 22:42
请关注TI社区，这里有相同的问题，配置寄存器时每个寄存器之间的时间间隔需要长一些。https://e2echina.ti ...

谢谢你的回复。这个我之前也看了，也增加了每两个寄存器配置之间的间隔时间，在软件复位和将MULXOUT置为readback模式之间的间隔为6000us，将MULXOUT置为readback模式后延时了6000us，其他的每个寄存器之间有20us的间隔，但还是读不出来~除了拆LMX2592了，其他都测过了，还是不行。
这是寄存器的配置，和芯片手册对了很多次，应该没有问题吧~请帮忙看看~
module flash_test
(
input       clock20M,
   input       RSTn,

output flash_clk,
   output flash_cs,
   output flash_datain,
   input  flash_dataout,

   output [4:0]spi_state,
   output [15:0] mydata_o,
   output [6:0] i_w,
   output reg [7:0] flash_addr,
   output reg [15:0] flash_data


);


/*******************************/

reg [6:0] i;
//reg [7:0] flash_addr;
//reg [15:0] flash_data;

reg [1:0] cmd_type;

reg [15:0] time_delay;

wire Done_Sig;
//wire [15:0] mydata_o;
wire myvalid_o;
//wire [4:0] spi_state;

assign i_w=i;

/*******************************/
//FLASH 擦除,Page Program,读取程序
/*******************************/
always @ ( posedge clock20M or negedge RSTn )
if( !RSTn )
begin
i <= 7'd0;
flash_addr <= 8'd0;
flash_data<=16'd0;
cmd_type <= 2'b00;
time_delay<=0;
end
   else
      case( i )

      7'd0://软件复位LMX器件
if( Done_Sig )
begin
i <= 1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b0000_0000;
flash_data<=16'b0010_0010_0001_1110;//16'b0000_0000_0000_0010;//
cmd_type <= 2'b10;
end

      7'd1:
if( time_delay<60000 )
begin
time_delay<=time_delay+1'b1;
cmd_type <= 2'b00;
end
else
begin
i <= 2;
time_delay<=0;
end

      7'd2://将MUX置为读出功能
if( Done_Sig )
begin
i <= 3;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b0000_0000;
flash_data<=16'b0010_0011_0001_1000;
cmd_type <= 2'b10;
end

      7'd3:
if( time_delay<60000 )
begin
time_delay<=time_delay+1'b1;
cmd_type <= 2'b00;
end
else
begin
i <= 4;
time_delay<=0;
end

// 7'd2://读状态寄存器0, 等待idle
// if( Done_Sig )
// begin
// i <= i + 1'b1;
// cmd_type <= 2'b00;
// end
// else
// begin
// flash_addr <= 8'b1000_0000;
// cmd_type <= 2'b11;
// end
//
//       7'd3:
// if( time_delay<8'd100 )
// begin
// time_delay<=time_delay+1'b1;
// cmd_type <= 2'b00;
// end
// else
// begin
// i <= i + 1'b1;
// time_delay<=0;
// end
// if( Done_Sig )
// begin
// i <= i + 1'b1;
// cmd_type <= 2'b00;
// end
// else
// begin
// flash_addr <= 8'b0000_0000;
// flash_data<=16'd0010_0100_0001_0000;
// cmd_type <= 2'b10;
// end

// 7'd3://读状态寄存器1, 等待idle
// if( Done_Sig )
// begin
// i <= i + 1'b1;
// cmd_type <= 2'b00;
// end
// else
// begin
// flash_addr <= 8'b1000_0001;
// cmd_type <= 2'b11;
// end

      7'd4://读取寄存器0
if( Done_Sig )
begin
i <= 5;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1000_0000;
cmd_type <= 2'b11;
end

      7'd5:
if( time_delay<200 )
begin
time_delay<=time_delay+1'b1;
cmd_type <= 2'b00;
end
else
begin
i <= 6;
time_delay<=0;
end

// 7'd5:
// if( Done_Sig )
// begin
// i <= i + 1'b1;
// cmd_type <= 2'b00;
// end
// else
// begin
// flash_addr <= 8'b1000_0011;
// cmd_type <= 2'b11;
// end

      7'd6:
if( Done_Sig )
begin
i <= 7;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1000_0100;
cmd_type <= 2'b11;
end

      7'd7:
if( time_delay<200 )
begin
time_delay<=time_delay+1'b1;
cmd_type <= 2'b00;
end
else
begin
i <= 8;//i + 1'b1;
time_delay<=0;
end

// 7'd7://读状态寄存器1, 等待idle
// if( Done_Sig )
// begin
// i <= i + 1'b1;
// cmd_type <= 2'b00;
// end
// else
// begin
// flash_addr <= 8'b1000_0101;
// cmd_type <= 2'b11;
// end

7'd8://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1000_0110;
cmd_type <= 2'b11;
end

      7'd9:
if( time_delay<200 )
begin
time_delay<=time_delay+1'b1;
cmd_type <= 2'b00;
end
else
begin
i <= i + 1'b1;
time_delay<=0;
end

// 7'd9://read 256byte
// if( Done_Sig )
// begin
// i <= i + 1'b1;
// cmd_type <= 2'b00;
// end
// else
// begin
// flash_addr <= 8'b1000_0111;
// cmd_type <= 2'b11;
// end

7'd10://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1000_1000;
cmd_type <= 2'b11;
end

7'd11://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1000_1001;
cmd_type <= 2'b11;
end

7'd12://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1000_1010;
cmd_type <= 2'b11;
end

7'd13://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1000_1011;
cmd_type <= 2'b11;
end

7'd14://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1000_1100;
cmd_type <= 2'b11;
end

7'd15://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1000_1101;
cmd_type <= 2'b11;
end

7'd16://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1000_1110;
cmd_type <= 2'b11;
end

7'd17://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1000_1111;
cmd_type <= 2'b11;
end

7'd18://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1001_0000;
cmd_type <= 2'b11;
end

7'd19://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1001_0001;
cmd_type <= 2'b11;
end

7'd20://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1001_0010;
cmd_type <= 2'b11;
end

7'd21://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1001_0011;
cmd_type <= 2'b11;
end

7'd22://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1001_0100;
cmd_type <= 2'b11;
end

7'd23://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1001_0101;
cmd_type <= 2'b11;
end

7'd24://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1001_0110;
cmd_type <= 2'b11;
end

7'd25://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1001_0111;
cmd_type <= 2'b11;
end

7'd26://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1001_1000;
cmd_type <= 2'b11;
end

7'd27://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1001_1001;
cmd_type <= 2'b11;
end

7'd28://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1001_1010;
cmd_type <= 2'b11;
end

7'd29://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1001_1011;
cmd_type <= 2'b11;
end

7'd30://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1001_1100;
cmd_type <= 2'b11;
end

7'd31://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1001_1101;
cmd_type <= 2'b11;
end

7'd32://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1001_1110;
cmd_type <= 2'b11;
end

7'd33://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1001_1111;
cmd_type <= 2'b11;
end

7'd34://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1010_0000;
cmd_type <= 2'b11;
end

7'd35://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1010_0001;
cmd_type <= 2'b11;
end

7'd36://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1010_0010;
cmd_type <= 2'b11;
end

7'd37://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1010_0011;
cmd_type <= 2'b11;
end

7'd38://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1010_0100;
cmd_type <= 2'b11;
end

7'd39://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1010_0101;
cmd_type <= 2'b11;
end

7'd40://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1010_0110;
cmd_type <= 2'b11;
end

7'd41://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1010_0111;
cmd_type <= 2'b11;
end

7'd42://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1010_1000;
cmd_type <= 2'b11;
end

7'd43://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1010_1001;
cmd_type <= 2'b11;
end

7'd44://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1010_1010;
cmd_type <= 2'b11;
end

7'd45://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1010_1011;
cmd_type <= 2'b11;
end

7'd46://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1010_1100;
cmd_type <= 2'b11;
end

7'd47://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1010_1101;
cmd_type <= 2'b11;
end

7'd48://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1010_1110;
cmd_type <= 2'b11;
end

7'd49://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1010_1111;
cmd_type <= 2'b11;
end

7'd50://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1011_0000;
cmd_type <= 2'b11;
end

7'd51://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1011_0001;
cmd_type <= 2'b11;
end

7'd52://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1011_0010;
cmd_type <= 2'b11;
end

7'd53://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1011_0011;
cmd_type <= 2'b11;
end

7'd54://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1011_0100;
cmd_type <= 2'b11;
end

7'd55://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1011_0101;
cmd_type <= 2'b11;
end

7'd56://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1011_0110;
cmd_type <= 2'b11;
end

7'd57://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1011_0111;
cmd_type <= 2'b11;
end

7'd58://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1011_1000;
cmd_type <= 2'b11;
end

7'd59://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1011_1001;
cmd_type <= 2'b11;
end

7'd60://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1011_1010;
cmd_type <= 2'b11;
end

7'd61://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1011_1011;
cmd_type <= 2'b11;
end

7'd62://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1011_1100;
cmd_type <= 2'b11;
end

7'd63://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1011_1101;
cmd_type <= 2'b11;
end

7'd64://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1011_1110;
cmd_type <= 2'b11;
end

7'd65://read 256byte
if( Done_Sig )
begin
i <= i + 1'b1;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1011_1111;
cmd_type <= 2'b11;
end

7'd66://read 256byte
if( Done_Sig )
begin
i <= 67;
cmd_type <= 2'b00;
end
else
begin
flash_addr <= 8'b1100_0000;
cmd_type <= 2'b11;
end

      7'd67://waitting
if( time_delay<200 )
begin
time_delay<=time_delay+1'b1;
cmd_type <= 2'b00;
end
else
begin
i <= 68;
time_delay<=0;
end

7'd68://idle
i <= 7'd4;
default:
i<=7'd68;

      endcase

/*****************************/
flash_spi U1 (
.flash_clk(flash_clk),
.flash_cs(flash_cs),
.flash_datain(flash_datain),
.flash_dataout(flash_dataout),

.clock20M(clock20M), //input clock
.flash_rstn(RSTn), //input reset
.cmd_type(cmd_type),  // flash command type
.Done_Sig(Done_Sig), //output done signal
.flash_addr(flash_addr), // input flash address
.flash_data(flash_data), // input flash data
.mydata_o(mydata_o), // output flash data
.myvalid_o(myvalid_o), // output flash data valid
.spi_state(spi_state)
);


endmodule

点赞 2019-4-26 17:06

4楼 flyuea123

麻烦把flash_spi发出来一起帮你看下，

点赞 2019-4-29 16:07

5楼 alan000345

跟着你们一起涨知识啦。

点赞 2019-4-30 09:24