FLASH MEMORY 的具体操作指南

ruibin_shu 2009-10-20 10:26 楼主

Typical storage methods are shown.
Read operation
A read operation starts with a command (00h), followed by five address cycles, followed by the read confirm (30h). After the read transfer time (tR) of approximately 25 μs, the data is loaded into the register and ready for output. Issuing the read enable (RE#) clock lets the NAND output the first byte corresponding to the column address specified in the address. Subsequent RE# transitions output successive locations. When RE# is high (not asserted), the I/O lines are tri-stated. Also, reading past the end of the device (byte 2112 or word 1056) results in reading invalid data. Random data can be directly accessed by issuing the (05h) command, two address cycles, and a (E0h) confirmation cycle. Once the page has been read from the array, this command provides rapid access to the data.
The NAND device actually has two registers: a data register and a cache register (Fig. 7). The Page read cache mode command lets you pipeline the next sequential access from the array while outputting the previously-accessed data. This double-buffered technique allows you to hide the read access time (tR). Data is first transferred from the NAND array to the data register. If the cache register is available (not busy), the data is quickly moved from the data register to the cache register. Once it's been transferred to the cache register, the data register is available and can start to load the next sequential page from the NAND array.

7. Shown is the page read cache mode.
A 33% performance improvement can be achieved on an 8-bit I/O device, resulting in up to 31 Mbytes/s of throughput. With the16-bit I/O device, throughput can be increased to 37 Mbytes/s, a 40% improvement over the normal Page read operation. Read cache can be especially useful during system boot-up, when large amounts of data are typically read from NAND and start-up time is critical.
Program page cache mode command
Program page cache mode provides performance improvement over normal Program page operations. This double-buffered technique lets the controller input data directly to the cache register and uses the data register as a holding register to supply the programming of the array. This frees the cache register so that the next sequential page operation can be loaded in parallel. In many applications, the programming time (tPROG) can be completely hidden. Like the page read cache mode command, the data register maintains the data through the entire programming cycle. This frees up the cache register so that it can start receiving the next page of data from the controller.
Read for internal data move (00h, 35h), or copy back, is another useful system-level command. It provides the ability to move data from one page to another internally without leaving the NAND device. The Read for internal data move operation transfers the data read from the NAND array to the cache register. It can then be programmed into another page of the NAND device. This is beneficial in cases where the controller needs to move data out of a block before erasing that block. It's also possible to modify the data read before the program operation starts. This could be useful if you wanted to change the data before programming. This feature allows data to be moved around within the NAND device without tying up the processor or the I/O bus.
Connecting NAND to a processor
There are significant advantages to selecting a processor or a controller with a built-in NAND interface. If this option isn't available, it's possible to design a glueless interface between the NAND and almost any processor. The main difference between NAND and NOR flash is the multiplexed address and data bus. This bus is used to specify commands, address, or data. The CLE signal specifies command cycles, while the ALE signal specifies address cycles. Using these two control signals, it's possible to select a command, address, or data cycle. Connecting ALE to the processor's address bit five and CLE to the processor's address bit four enables the selection of either command, address, or data simply by changing the address that the processor outputs. This allows CLE and ALE to be asserted automatically at the appropriate time.
To supply a command, the processor outputs the intended command on the data bus and output address 0010h. To supply any number of address cycles, the processor simply needs to output the intended NAND address sequence to processor address 0020h. Note that many processors can specify several timing parameters around the processor's write signal, which is critical for proper timing. Using this technique, you can access commands, address, and data directly from the processor without any glue logic. In this case, ECC would have to be handled in the software.