FCR的最低位是使能/禁止FIFO的。模式选择是FCR【3】——但是奇怪的是我这个两个模式我都试过了还是同样的结果。

6.7 Hardware/software and time-out interrupts
The interrupts are enabled by IER[0-3]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the
SC16C652 will issue a Transmit Holding Register interrupt. This interrupt must be
serviced prior to continuing operations. The LSR register provides the current
singular highest priority interrupt only. It could be noted that CTS and RTS interrupts
have lowest interrupt priority. A condition can exist where a higher priority interrupt
may mask the lower priority CTS/RTS interrupt(s). Only after servicing the higher
pending interrupt will the lower priority CTS/RTS interrupt(s) be re?ected in the status
register. Servicing the interrupt without investigating further interrupt conditions can
result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[3]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C652 FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time,
including data information length, start bit, parity bit, and the size of stop bit, i.e., 1×,
1.5×, or 2× bit times.

papapa123123 老兄，你电路是怎么画的？从下面的手册说明中有这个超时中断发生会在RXRDY 引脚上表现出来，我的电路没有接这个引脚，只接了INTA、INTB引脚，难道是这个问题？
Receive operation in mode ‘1’: When the SC16C652 is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been
reached, or a Receive Time-Out has occurred, the RXRDY pin will go to
a logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO.

The SC16C652 FIFO trigger level provides additional ?exibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in
the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY
output pins. ——DMA模式 （通过FCR[3])设置）在RXRDY and TXRDY
output pins.反映，那么我的电路岂不是画错了？请问各位的电路是怎么样的？

pHWHead->FCR = 0x81;// work well 2009.04.21
汗，我把上面的换成下面的就只能接受到一个字节了，难道FIFO不能设置过大？
pHWHead->FCR = 0xC0;  //fifo tx rx = max len  FCR[3]--DMA select mode

我把pHWHead->FCR = 0xC1;试试。

我把pHWHead->FCR = 0xC1果然可以了。

汗，这个东西居然是程序执行先后问题，就是FIFO使能必须在其他设置之前——我昨天已经首先复位了？怎么搞的，昨天却不行，不管怎么样，总算解决了。

恭喜恭喜

先使能后改大小？有这样限制？看来以前都是直接赋值反而没问题。

你们的估计没有，我的是SC16C652和16554还是有点区别的，你们的发送FIFO是默认大小的。我的可以设置的。

还有我的数据手册上明显说明：
FCR[0] FIFO enable.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO. This bit must be a
‘1’ when other FCR bits are written to, or they will not be
programmed.

那个串口驱动我是根据16C554改来的，所以一直没有注意这个问题。

加分100
xumercury 老兄还帮我看数据手册。

恭喜恭喜 .刚一上来就看到你解决了/

哈哈。兄弟。关键时刻要坚持下就通了。。。Thanks God.

哎，我碰到的是 一次发送100多个字节，就会丢10几个，如果发送的字节数少就不会丢，
后来发现是超限错误，LSR[1]被置位了。

怎么才能避免了？请教大家