[其他芯片] 【国产FPGA 正点原子DFPGL22G开发板】四、检波器代码编写

Jimmy_Arareb 2023-1-25 23:22 楼主

# 四、 检波器代码编写

[TOC]

## 1.旋转变压器原理

### 旋转变压器简介

旋转变压器是一种电磁式角度传感器，用来测量旋转轴的角位置和角速度，具有结构简单，可靠性高，耐振动、耐高低温的特点，广泛应用于以航空航天为代表的国防及工业产品中。

> 旋转变压器结构示意图

近年来电动汽车快速发展，旋转变压器由于其适用于汽车行驶过程中的恶劣工况的独特优势，开始进入民用领域。

旋转变压器的工作原理与普通变压器类似，在初级线圈通入励磁电压，通过旋转改变耦合进入次级绕组的磁链，对次级输出电压进行调制，得到包含角度信息的调幅信号。其中次级绕组有两组，分别称为正、余弦绕组，输出两路正交角度信号。通过对两路输出信号进行检波和鉴相，可以提取出当前转轴的角度和角速度。

### 数学模型

在理想条件下，旋转变压器的数学模型为：

其中$V_r$是激磁信号，$V_a$是余弦绕组输出，$V_b$是正弦绕组输出，$\omega$为激磁角频率，$\theta$为转轴角位置。

> 旋转变压器信号示意图

### RDC介绍

旋转变压器数字变换器(Resolver to Digital Converter, RDC)可以提供旋转变压器所需的激磁信号，并将旋转变压器输出的正余弦调制信号转化为角位置和角速度的数字信号并输出至数字控制器。

对于一般精度要求的应用，通常选用成品RDC芯片，如ADI公司的AD2S1210等。对于特殊应用，可以采用软件方式实现定制的RDC算法，有效补偿各类误差。软件实现RDC一般使用DSP或FPGA，其中DSP开发相对容易，但并行化程度与FPGA相比有一定差距，对于较为复杂的补偿算法不能满足实时性要求。FPGA开发周期较长，但硬件配置更加灵活，可以实时完成复杂算法。

RDC一般由三大主要部分组成：
1. 激磁信号源
   * 提供激磁信号，驱动电流放大器。
2. 检波器
   * 从正余弦调制信号中提取包络。
3. 鉴相器
   * 从正余弦包络中提取角度和角速度。

## 2.检波器原理

### 检波方法

旋转变压器的输出本质上是双边带调幅信号。激磁信号由FPGA自身通过DDS及SPWM给出，可以直接进行相干解调。

使用乘积检波，将载波信号与两路旋变输出信号相乘，得到包含两个频率分量的信号。以正弦输出为例：

相乘后的信号经过低通滤波器后滤除高频部分：

得到包络信号：

余弦输出同理，归一化后得到两路正余弦包络，检波完成。

## 3.检波器实现

### 混频器

混频器直接例化PDS提供的乘法器IP即可，注意定点数相乘后的小数位数为相加关系。

为了节省APM资源，使用状态机控制两路信号依次进入乘法器，进行运算后输出。

```verilog
module mixer (
    input clk_50m,
    input rst_n,

input [15:0] sync_carrier,
    input [15:0] ch_sin,
    input [15:0] ch_cos,
    input        data_valid,

output reg [15:0] sin_mixed,
    output reg [15:0] cos_mixed,
    output reg        data_ready
);

reg  [15:0] ch_in = 16'b0;
    wire [31:0] mult_out;

detector_multiplier u_detector_multiplier (
        .a  (sync_carrier),  // input [15:0]
        .b  (ch_in),         // input [15:0]
        .clk(clk_50m),       // input
        .rst(~rst_n),        // input
        .ce (1'b1),          // input
        .p  (mult_out)       // output [31:0]
    );

localparam IDLE = 6'b1 << 0;
 localparam SIN_IN = 6'b1 << 1;
 localparam COS_IN = 6'b1 << 2;
 localparam SIN_OUT = 6'b1 << 3;
 localparam COS_OUT = 6'b1 << 4;
 localparam DONE = 6'b1 << 5;

reg [5:0] state = IDLE;

//状态转移
 always @(posedge clk_50m) begin
 if (~rst_n) begin
 state <= IDLE;
 end else begin
 case (state)
 IDLE: begin
 if (data_valid) begin
 state <= SIN_IN;
 end else begin
 state <= IDLE;
 end
 end
 SIN_IN: begin
 state <= COS_IN;
 end
 COS_IN: begin
 state <= SIN_OUT;
 end
 SIN_OUT: begin
 state <= COS_OUT;
 end
 COS_OUT: begin
 state <= DONE;
 end
 DONE: begin
 state <= IDLE;
 end
 default: begin
 state <= IDLE;
 end
 endcase
 end
 end

//数据输入输出
 always @(posedge clk_50m) begin
 case (state)
 SIN_IN: begin
 ch_in <= ch_sin;
 end
 COS_IN: begin
 ch_in <= ch_cos;
 end
 SIN_OUT: begin
 sin_mixed <= mult_out[30:15];
 end
 COS_OUT: begin
 cos_mixed <= mult_out[30:15];
 end
 default: begin
 ch_in <= ch_in;
 sin_mixed <= sin_mixed;
 cos_mixed <= cos_mixed;
 end
 endcase
 end

//计算完成标志
 always @(posedge clk_50m) begin
 if (~rst_n) begin
 data_ready <= 1'b0;
 end else if (state == DONE) begin
 data_ready <= 1'b1;
 end else begin
 data_ready <= 1'b0;
 end
 end

endmodule
```

### 滤波器

FIR滤波器可以保持线性相频特性，便于后续的补偿需要。利用Matlab的滤波器设计工具可以方便地设计数字滤波器，选取的滤波器参数如图所示：

FPGA一般使用定点数进行计算，需要对滤波器进行定点化处理。

设计完成后使用Simulink对滤波器进行验证，效果良好。

使用HDL Coder生成verilog代码，选择串行结构以节约APM资源。由于Matlab生成的代码只支持连续工作，使用前需要添加输入输出控制信号，保持滤波器计算与采样周期一致。

```verilog
// -------------------------------------------------------------
//
// Module: filter_detector
// Generated by MATLAB(R) 9.13 and Filter Design HDL Coder 3.1.12.
// Generated on: 2023-01-23 16:37:09
// -------------------------------------------------------------

// -------------------------------------------------------------
// HDL Code Generation Options:
//
// ResetType: Synchronous
// FIRAdderStyle: tree
// MultiplierOutputPipeline: 1
// OptimizeForHDL: on
// ClockInputPort: clk_50m
// ResetInputPort: rst_n
// TargetDirectory: D:\PGL22G\envelope_detector\matlab
// AddPipelineRegisters: on
// Name: filter_detector
// ResetAssertedLevel: Active-low
// SerialPartition: [12  12  12  11]
// TargetLanguage: Verilog
// TestBenchStimulus: impulse step ramp chirp noise

// -------------------------------------------------------------
// HDL Implementation    : Partly Serial
// Folding Factor        : 12
// -------------------------------------------------------------

`timescale 1 ns / 1 ns

module filter_detector
               (
                clk_50m,
                clk_enable,
                data_valid,
                rst_n,
                filter_in,
                filter_out,
                data_ready
                );

input   clk_50m; 
  input   clk_enable; 
  input   data_valid;
  input   rst_n; 
  input   signed [15:0] filter_in; //sfix16_En15
  output  signed [34:0] filter_out; //sfix35_En34
  output reg data_ready;

////////////////////////////////////////////////////////////////
//Module Architecture: filter_detector
////////////////////////////////////////////////////////////////
  // Local Functions
  // Type Definitions
  // Constants
  parameter signed [15:0] coeff1 = 16'b0000001000001001; //sfix16_En19
  parameter signed [15:0] coeff2 = 16'b0000001001001011; //sfix16_En19
  parameter signed [15:0] coeff3 = 16'b0000001110000000; //sfix16_En19
  parameter signed [15:0] coeff4 = 16'b0000010100001011; //sfix16_En19
  parameter signed [15:0] coeff5 = 16'b0000011011110101; //sfix16_En19
  parameter signed [15:0] coeff6 = 16'b0000100101000101; //sfix16_En19
  parameter signed [15:0] coeff7 = 16'b0000101111111110; //sfix16_En19
  parameter signed [15:0] coeff8 = 16'b0000111100100001; //sfix16_En19
  parameter signed [15:0] coeff9 = 16'b0001001010101001; //sfix16_En19
  parameter signed [15:0] coeff10 = 16'b0001011010010000; //sfix16_En19
  parameter signed [15:0] coeff11 = 16'b0001101011001010; //sfix16_En19
  parameter signed [15:0] coeff12 = 16'b0001111101001000; //sfix16_En19
  parameter signed [15:0] coeff13 = 16'b0010001111110111; //sfix16_En19
  parameter signed [15:0] coeff14 = 16'b0010100011000000; //sfix16_En19
  parameter signed [15:0] coeff15 = 16'b0010110110001010; //sfix16_En19
  parameter signed [15:0] coeff16 = 16'b0011001000111010; //sfix16_En19
  parameter signed [15:0] coeff17 = 16'b0011011010110011; //sfix16_En19
  parameter signed [15:0] coeff18 = 16'b0011101011011010; //sfix16_En19
  parameter signed [15:0] coeff19 = 16'b0011111010010011; //sfix16_En19
  parameter signed [15:0] coeff20 = 16'b0100000111000101; //sfix16_En19
  parameter signed [15:0] coeff21 = 16'b0100010001011010; //sfix16_En19
  parameter signed [15:0] coeff22 = 16'b0100011001000000; //sfix16_En19
  parameter signed [15:0] coeff23 = 16'b0100011101101001; //sfix16_En19
  parameter signed [15:0] coeff24 = 16'b0100011111001101; //sfix16_En19
  parameter signed [15:0] coeff25 = 16'b0100011101101001; //sfix16_En19
  parameter signed [15:0] coeff26 = 16'b0100011001000000; //sfix16_En19
  parameter signed [15:0] coeff27 = 16'b0100010001011010; //sfix16_En19
  parameter signed [15:0] coeff28 = 16'b0100000111000101; //sfix16_En19
  parameter signed [15:0] coeff29 = 16'b0011111010010011; //sfix16_En19
  parameter signed [15:0] coeff30 = 16'b0011101011011010; //sfix16_En19
  parameter signed [15:0] coeff31 = 16'b0011011010110011; //sfix16_En19
  parameter signed [15:0] coeff32 = 16'b0011001000111010; //sfix16_En19
  parameter signed [15:0] coeff33 = 16'b0010110110001010; //sfix16_En19
  parameter signed [15:0] coeff34 = 16'b0010100011000000; //sfix16_En19
  parameter signed [15:0] coeff35 = 16'b0010001111110111; //sfix16_En19
  parameter signed [15:0] coeff36 = 16'b0001111101001000; //sfix16_En19
  parameter signed [15:0] coeff37 = 16'b0001101011001010; //sfix16_En19
  parameter signed [15:0] coeff38 = 16'b0001011010010000; //sfix16_En19
  parameter signed [15:0] coeff39 = 16'b0001001010101001; //sfix16_En19
  parameter signed [15:0] coeff40 = 16'b0000111100100001; //sfix16_En19
  parameter signed [15:0] coeff41 = 16'b0000101111111110; //sfix16_En19
  parameter signed [15:0] coeff42 = 16'b0000100101000101; //sfix16_En19
  parameter signed [15:0] coeff43 = 16'b0000011011110101; //sfix16_En19
  parameter signed [15:0] coeff44 = 16'b0000010100001011; //sfix16_En19
  parameter signed [15:0] coeff45 = 16'b0000001110000000; //sfix16_En19
  parameter signed [15:0] coeff46 = 16'b0000001001001011; //sfix16_En19
  parameter signed [15:0] coeff47 = 16'b0000001000001001; //sfix16_En19

// Signals
  reg  [3:0] cur_count; // ufix4
  wire phase_12; // boolean
  wire phase_1; // boolean
  wire phase_1_1; // boolean
  reg  signed [15:0] delay_pipeline [0:46] ; // sfix16_En15
  wire signed [15:0] inputmux_1; // sfix16_En15
  wire signed [15:0] inputmux_2; // sfix16_En15
  wire signed [15:0] inputmux_3; // sfix16_En15
  wire signed [15:0] inputmux_4; // sfix16_En15
  reg  signed [34:0] acc_final; // sfix35_En34
  reg  signed [34:0] acc_out_1; // sfix35_En34
  wire signed [30:0] product_1; // sfix31_En34
  wire signed [15:0] product_1_mux; // sfix16_En19
  reg  signed [31:0] product_1_pipe; // sfix32_En34
  wire signed [34:0] prod_typeconvert_1; // sfix35_En34
  wire signed [34:0] acc_sum_1; // sfix35_En34
  wire signed [34:0] acc_in_1; // sfix35_En34
  wire signed [34:0] add_signext; // sfix35_En34
  wire signed [34:0] add_signext_1; // sfix35_En34
  wire signed [35:0] add_temp; // sfix36_En34
  reg  signed [34:0] acc_out_2; // sfix35_En34
  wire signed [30:0] product_2; // sfix31_En34
  wire signed [15:0] product_2_mux; // sfix16_En19
  reg  signed [31:0] product_2_pipe; // sfix32_En34
  wire signed [34:0] prod_typeconvert_2; // sfix35_En34
  wire signed [34:0] acc_sum_2; // sfix35_En34
  wire signed [34:0] acc_in_2; // sfix35_En34
  wire signed [34:0] add_signext_2; // sfix35_En34
  wire signed [34:0] add_signext_3; // sfix35_En34
  wire signed [35:0] add_temp_1; // sfix36_En34
  reg  signed [34:0] acc_out_3; // sfix35_En34
  wire signed [30:0] product_3; // sfix31_En34
  wire signed [15:0] product_3_mux; // sfix16_En19
  reg  signed [31:0] product_3_pipe; // sfix32_En34
  wire signed [34:0] prod_typeconvert_3; // sfix35_En34
  wire signed [34:0] acc_sum_3; // sfix35_En34
  wire signed [34:0] acc_in_3; // sfix35_En34
  wire signed [34:0] add_signext_4; // sfix35_En34
  wire signed [34:0] add_signext_5; // sfix35_En34
  wire signed [35:0] add_temp_2; // sfix36_En34
  reg  signed [34:0] acc_out_4; // sfix35_En34
  wire signed [30:0] product_4; // sfix31_En34
  wire signed [15:0] product_4_mux; // sfix16_En19
  reg  signed [31:0] product_4_pipe; // sfix32_En34
  wire signed [34:0] prod_typeconvert_4; // sfix35_En34
  wire signed [34:0] acc_sum_4; // sfix35_En34
  wire signed [34:0] acc_in_4; // sfix35_En34
  wire signed [34:0] add_signext_6; // sfix35_En34
  wire signed [34:0] add_signext_7; // sfix35_En34
  wire signed [35:0] add_temp_3; // sfix36_En34
  wire signed [34:0] sumvector1 [0:1] ; // sfix35_En34
  wire signed [34:0] add_signext_8; // sfix35_En34
  wire signed [34:0] add_signext_9; // sfix35_En34
  wire signed [35:0] add_temp_4; // sfix36_En34
  wire signed [34:0] add_signext_10; // sfix35_En34
  wire signed [34:0] add_signext_11; // sfix35_En34
  wire signed [35:0] add_temp_5; // sfix36_En34
  reg  signed [34:0] sumdelay_pipeline1 [0:1] ; // sfix35_En34
  wire signed [34:0] sum2; // sfix35_En34
  wire signed [34:0] add_signext_12; // sfix35_En34
  wire signed [34:0] add_signext_13; // sfix35_En34
  wire signed [35:0] add_temp_6; // sfix36_En34

// Block Statements
 always @ (posedge clk_50m)
 begin: Counter_process
 if (rst_n == 1'b0) begin
 cur_count <= 4'b1111;
 end
 else begin
 if (clk_enable == 1'b1) begin
 if (cur_count >= 4'b1111) begin
 if (data_valid == 1'b1) begin
 cur_count <= 4'b0000;
 end else begin
 cur_count <= cur_count;
 end
 end
 else begin
 cur_count <= cur_count + 4'b0001;
 end
 end
 end
 end // Counter_process

assign  phase_12 = (cur_count == 4'b1100 && clk_enable == 1'b1) ? 1'b1 : 1'b0;

assign  phase_1 = (cur_count == 4'b0001 && clk_enable == 1'b1) ? 1'b1 : 1'b0;

assign phase_1_1 = (((cur_count == 4'b0001) ||
                       (cur_count == 4'b0010)  ||
                       (cur_count == 4'b0011)  ||
                       (cur_count == 4'b0100)  ||
                       (cur_count == 4'b0101)  ||
                       (cur_count == 4'b0110)  ||
                       (cur_count == 4'b0111)  ||
                       (cur_count == 4'b1000)  ||
                       (cur_count == 4'b1001)  ||
                       (cur_count == 4'b1010)  ||
                       (cur_count == 4'b1011)) && clk_enable == 1'b1) ? 1'b1 : 1'b0;

always @( posedge clk_50m)
 begin: Delay_Pipeline_process
 if (rst_n == 1'b0) begin
 delay_pipeline[0] <= 0;
 delay_pipeline[1] <= 0;
 delay_pipeline[2] <= 0;
 delay_pipeline[3] <= 0;
 delay_pipeline[4] <= 0;
 delay_pipeline[5] <= 0;
 delay_pipeline[6] <= 0;
 delay_pipeline[7] <= 0;
 delay_pipeline[8] <= 0;
 delay_pipeline[9] <= 0;
 delay_pipeline[10] <= 0;
 delay_pipeline[11] <= 0;
 delay_pipeline[12] <= 0;
 delay_pipeline[13] <= 0;
 delay_pipeline[14] <= 0;
 delay_pipeline[15] <= 0;
 delay_pipeline[16] <= 0;
 delay_pipeline[17] <= 0;
 delay_pipeline[18] <= 0;
 delay_pipeline[19] <= 0;
 delay_pipeline[20] <= 0;
 delay_pipeline[21] <= 0;
 delay_pipeline[22] <= 0;
 delay_pipeline[23] <= 0;
 delay_pipeline[24] <= 0;
 delay_pipeline[25] <= 0;
 delay_pipeline[26] <= 0;
 delay_pipeline[27] <= 0;
 delay_pipeline[28] <= 0;
 delay_pipeline[29] <= 0;
 delay_pipeline[30] <= 0;
 delay_pipeline[31] <= 0;
 delay_pipeline[32] <= 0;
 delay_pipeline[33] <= 0;
 delay_pipeline[34] <= 0;
 delay_pipeline[35] <= 0;
 delay_pipeline[36] <= 0;
 delay_pipeline[37] <= 0;
 delay_pipeline[38] <= 0;
 delay_pipeline[39] <= 0;
 delay_pipeline[40] <= 0;
 delay_pipeline[41] <= 0;
 delay_pipeline[42] <= 0;
 delay_pipeline[43] <= 0;
 delay_pipeline[44] <= 0;
 delay_pipeline[45] <= 0;
 delay_pipeline[46] <= 0;
 end
 else begin
 if (data_valid == 1'b1) begin
 delay_pipeline[0] <= filter_in;
 delay_pipeline[1] <= delay_pipeline[0];
 delay_pipeline[2] <= delay_pipeline[1];
 delay_pipeline[3] <= delay_pipeline[2];
 delay_pipeline[4] <= delay_pipeline[3];
 delay_pipeline[5] <= delay_pipeline[4];
 delay_pipeline[6] <= delay_pipeline[5];
 delay_pipeline[7] <= delay_pipeline[6];
 delay_pipeline[8] <= delay_pipeline[7];
 delay_pipeline[9] <= delay_pipeline[8];
 delay_pipeline[10] <= delay_pipeline[9];
 delay_pipeline[11] <= delay_pipeline[10];
 delay_pipeline[12] <= delay_pipeline[11];
 delay_pipeline[13] <= delay_pipeline[12];
 delay_pipeline[14] <= delay_pipeline[13];
 delay_pipeline[15] <= delay_pipeline[14];
 delay_pipeline[16] <= delay_pipeline[15];
 delay_pipeline[17] <= delay_pipeline[16];
 delay_pipeline[18] <= delay_pipeline[17];
 delay_pipeline[19] <= delay_pipeline[18];
 delay_pipeline[20] <= delay_pipeline[19];
 delay_pipeline[21] <= delay_pipeline[20];
 delay_pipeline[22] <= delay_pipeline[21];
 delay_pipeline[23] <= delay_pipeline[22];
 delay_pipeline[24] <= delay_pipeline[23];
 delay_pipeline[25] <= delay_pipeline[24];
 delay_pipeline[26] <= delay_pipeline[25];
 delay_pipeline[27] <= delay_pipeline[26];
 delay_pipeline[28] <= delay_pipeline[27];
 delay_pipeline[29] <= delay_pipeline[28];
 delay_pipeline[30] <= delay_pipeline[29];
 delay_pipeline[31] <= delay_pipeline[30];
 delay_pipeline[32] <= delay_pipeline[31];
 delay_pipeline[33] <= delay_pipeline[32];
 delay_pipeline[34] <= delay_pipeline[33];
 delay_pipeline[35] <= delay_pipeline[34];
 delay_pipeline[36] <= delay_pipeline[35];
 delay_pipeline[37] <= delay_pipeline[36];
 delay_pipeline[38] <= delay_pipeline[37];
 delay_pipeline[39] <= delay_pipeline[38];
 delay_pipeline[40] <= delay_pipeline[39];
 delay_pipeline[41] <= delay_pipeline[40];
 delay_pipeline[42] <= delay_pipeline[41];
 delay_pipeline[43] <= delay_pipeline[42];
 delay_pipeline[44] <= delay_pipeline[43];
 delay_pipeline[45] <= delay_pipeline[44];
 delay_pipeline[46] <= delay_pipeline[45];
 end
 end
 end // Delay_Pipeline_process

assign inputmux_1 = (cur_count == 4'b0000) ? delay_pipeline[0] :
                     (cur_count == 4'b0001) ? delay_pipeline[1] :
                     (cur_count == 4'b0010) ? delay_pipeline[2] :
                     (cur_count == 4'b0011) ? delay_pipeline[3] :
                     (cur_count == 4'b0100) ? delay_pipeline[4] :
                     (cur_count == 4'b0101) ? delay_pipeline[5] :
                     (cur_count == 4'b0110) ? delay_pipeline[6] :
                     (cur_count == 4'b0111) ? delay_pipeline[7] :
                     (cur_count == 4'b1000) ? delay_pipeline[8] :
                     (cur_count == 4'b1001) ? delay_pipeline[9] :
                     (cur_count == 4'b1010) ? delay_pipeline[10] :
                     delay_pipeline[11];

assign inputmux_2 = (cur_count == 4'b0000) ? delay_pipeline[12] :
                     (cur_count == 4'b0001) ? delay_pipeline[13] :
                     (cur_count == 4'b0010) ? delay_pipeline[14] :
                     (cur_count == 4'b0011) ? delay_pipeline[15] :
                     (cur_count == 4'b0100) ? delay_pipeline[16] :
                     (cur_count == 4'b0101) ? delay_pipeline[17] :
                     (cur_count == 4'b0110) ? delay_pipeline[18] :
                     (cur_count == 4'b0111) ? delay_pipeline[19] :
                     (cur_count == 4'b1000) ? delay_pipeline[20] :
                     (cur_count == 4'b1001) ? delay_pipeline[21] :
                     (cur_count == 4'b1010) ? delay_pipeline[22] :
                     delay_pipeline[23];

assign inputmux_3 = (cur_count == 4'b0000) ? delay_pipeline[24] :
                     (cur_count == 4'b0001) ? delay_pipeline[25] :
                     (cur_count == 4'b0010) ? delay_pipeline[26] :
                     (cur_count == 4'b0011) ? delay_pipeline[27] :
                     (cur_count == 4'b0100) ? delay_pipeline[28] :
                     (cur_count == 4'b0101) ? delay_pipeline[29] :
                     (cur_count == 4'b0110) ? delay_pipeline[30] :
                     (cur_count == 4'b0111) ? delay_pipeline[31] :
                     (cur_count == 4'b1000) ? delay_pipeline[32] :
                     (cur_count == 4'b1001) ? delay_pipeline[33] :
                     (cur_count == 4'b1010) ? delay_pipeline[34] :
                     delay_pipeline[35];

assign inputmux_4 = (cur_count == 4'b0000) ? delay_pipeline[36] :
                     (cur_count == 4'b0001) ? delay_pipeline[37] :
                     (cur_count == 4'b0010) ? delay_pipeline[38] :
                     (cur_count == 4'b0011) ? delay_pipeline[39] :
                     (cur_count == 4'b0100) ? delay_pipeline[40] :
                     (cur_count == 4'b0101) ? delay_pipeline[41] :
                     (cur_count == 4'b0110) ? delay_pipeline[42] :
                     (cur_count == 4'b0111) ? delay_pipeline[43] :
                     (cur_count == 4'b1000) ? delay_pipeline[44] :
                     (cur_count == 4'b1001) ? delay_pipeline[45] :
                     delay_pipeline[46];

//   ------------------ Serial partition # 1 ------------------

assign product_1_mux = (cur_count == 4'b0000) ? coeff1 :
 (cur_count == 4'b0001) ? coeff2 :
 (cur_count == 4'b0010) ? coeff3 :
 (cur_count == 4'b0011) ? coeff4 :
 (cur_count == 4'b0100) ? coeff5 :
 (cur_count == 4'b0101) ? coeff6 :
 (cur_count == 4'b0110) ? coeff7 :
 (cur_count == 4'b0111) ? coeff8 :
 (cur_count == 4'b1000) ? coeff9 :
 (cur_count == 4'b1001) ? coeff10 :
 (cur_count == 4'b1010) ? coeff11 :
 coeff12;
 always @ (posedge clk_50m)
 begin: temp_process1
 if (rst_n == 1'b0) begin
 product_1_pipe <= 0;
 end
 else begin
 if (clk_enable == 1'b1) begin

product_1_pipe <= inputmux_1 * product_1_mux;

end
      end
    end // temp_process1

assign product_1 = product_1_pipe[30:0];

assign prod_typeconvert_1 = $signed({{4{product_1[30]}}, product_1});

assign add_signext = prod_typeconvert_1;
  assign add_signext_1 = acc_out_1;
  assign add_temp = add_signext + add_signext_1;
  assign acc_sum_1 = add_temp[34:0];

assign acc_in_1 = (phase_1 == 1'b1) ? prod_typeconvert_1 :
                   acc_sum_1;

always @ ( posedge clk_50m)
 begin: Acc_reg_1_process
 if (rst_n == 1'b0) begin
 acc_out_1 <= 0;
 end
 else begin
 if (clk_enable == 1'b1) begin
 acc_out_1 <= acc_in_1;
 end
 end
 end // Acc_reg_1_process

//   ------------------ Serial partition # 2 ------------------

assign product_2_mux = (cur_count == 4'b0000) ? coeff13 :
 (cur_count == 4'b0001) ? coeff14 :
 (cur_count == 4'b0010) ? coeff15 :
 (cur_count == 4'b0011) ? coeff16 :
 (cur_count == 4'b0100) ? coeff17 :
 (cur_count == 4'b0101) ? coeff18 :
 (cur_count == 4'b0110) ? coeff19 :
 (cur_count == 4'b0111) ? coeff20 :
 (cur_count == 4'b1000) ? coeff21 :
 (cur_count == 4'b1001) ? coeff22 :
 (cur_count == 4'b1010) ? coeff23 :
 coeff24;
 always @ (posedge clk_50m)
 begin: temp_process2
 if (rst_n == 1'b0) begin
 product_2_pipe <= 0;
 end
 else begin
 if (clk_enable == 1'b1) begin

product_2_pipe <= inputmux_2 * product_2_mux;

end
      end
    end // temp_process2

assign product_2 = product_2_pipe[30:0];

assign prod_typeconvert_2 = $signed({{4{product_2[30]}}, product_2});

assign add_signext_2 = prod_typeconvert_2;
  assign add_signext_3 = acc_out_2;
  assign add_temp_1 = add_signext_2 + add_signext_3;
  assign acc_sum_2 = add_temp_1[34:0];

assign acc_in_2 = (phase_1 == 1'b1) ? prod_typeconvert_2 :
                   acc_sum_2;

always @ ( posedge clk_50m)
 begin: Acc_reg_2_process
 if (rst_n == 1'b0) begin
 acc_out_2 <= 0;
 end
 else begin
 if (clk_enable == 1'b1) begin
 acc_out_2 <= acc_in_2;
 end
 end
 end // Acc_reg_2_process

//   ------------------ Serial partition # 3 ------------------

assign product_3_mux = (cur_count == 4'b0000) ? coeff25 :
 (cur_count == 4'b0001) ? coeff26 :
 (cur_count == 4'b0010) ? coeff27 :
 (cur_count == 4'b0011) ? coeff28 :
 (cur_count == 4'b0100) ? coeff29 :
 (cur_count == 4'b0101) ? coeff30 :
 (cur_count == 4'b0110) ? coeff31 :
 (cur_count == 4'b0111) ? coeff32 :
 (cur_count == 4'b1000) ? coeff33 :
 (cur_count == 4'b1001) ? coeff34 :
 (cur_count == 4'b1010) ? coeff35 :
 coeff36;
 always @ (posedge clk_50m)
 begin: temp_process3
 if (rst_n == 1'b0) begin
 product_3_pipe <= 0;
 end
 else begin
 if (clk_enable == 1'b1) begin

product_3_pipe <= inputmux_3 * product_3_mux;

end
      end
    end // temp_process3

assign product_3 = product_3_pipe[30:0];

assign prod_typeconvert_3 = $signed({{4{product_3[30]}}, product_3});

assign add_signext_4 = prod_typeconvert_3;
  assign add_signext_5 = acc_out_3;
  assign add_temp_2 = add_signext_4 + add_signext_5;
  assign acc_sum_3 = add_temp_2[34:0];

assign acc_in_3 = (phase_1 == 1'b1) ? prod_typeconvert_3 :
                   acc_sum_3;

always @ ( posedge clk_50m)
 begin: Acc_reg_3_process
 if (rst_n == 1'b0) begin
 acc_out_3 <= 0;
 end
 else begin
 if (clk_enable == 1'b1) begin
 acc_out_3 <= acc_in_3;
 end
 end
 end // Acc_reg_3_process

//   ------------------ Serial partition # 4 ------------------

assign product_4_mux = (cur_count == 4'b0000) ? coeff37 :
 (cur_count == 4'b0001) ? coeff38 :
 (cur_count == 4'b0010) ? coeff39 :
 (cur_count == 4'b0011) ? coeff40 :
 (cur_count == 4'b0100) ? coeff41 :
 (cur_count == 4'b0101) ? coeff42 :
 (cur_count == 4'b0110) ? coeff43 :
 (cur_count == 4'b0111) ? coeff44 :
 (cur_count == 4'b1000) ? coeff45 :
 (cur_count == 4'b1001) ? coeff46 :
 coeff47;
 always @ (posedge clk_50m)
 begin: temp_process4
 if (rst_n == 1'b0) begin
 product_4_pipe <= 0;
 end
 else begin
 if (clk_enable == 1'b1) begin

product_4_pipe <= inputmux_4 * product_4_mux;

end
      end
    end // temp_process4

assign product_4 = product_4_pipe[30:0];

assign prod_typeconvert_4 = $signed({{4{product_4[30]}}, product_4});

assign add_signext_6 = prod_typeconvert_4;
  assign add_signext_7 = acc_out_4;
  assign add_temp_3 = add_signext_6 + add_signext_7;
  assign acc_sum_4 = add_temp_3[34:0];

assign acc_in_4 = (phase_1 == 1'b1) ? prod_typeconvert_4 :
                   acc_sum_4;

always @ ( posedge clk_50m)
 begin: Acc_reg_4_process
 if (rst_n == 1'b0) begin
 acc_out_4 <= 0;
 end
 else begin
 if (phase_1_1 == 1'b1) begin
 acc_out_4 <= acc_in_4;
 end
 end
 end // Acc_reg_4_process

assign add_signext_8 = acc_out_1;
  assign add_signext_9 = acc_out_2;
  assign add_temp_4 = add_signext_8 + add_signext_9;
  assign sumvector1[0] = add_temp_4[34:0];

assign add_signext_10 = acc_out_3;
  assign add_signext_11 = acc_out_4;
  assign add_temp_5 = add_signext_10 + add_signext_11;
  assign sumvector1[1] = add_temp_5[34:0];

always @ ( posedge clk_50m)
 begin: sumdelay_pipeline_process1
 if (rst_n == 1'b0) begin
 sumdelay_pipeline1[0] <= 0;
 sumdelay_pipeline1[1] <= 0;
 end
 else begin
 if (clk_enable == 1'b1) begin
 sumdelay_pipeline1[0] <= sumvector1[0];
 sumdelay_pipeline1[1] <= sumvector1[1];
 end
 end
 end // sumdelay_pipeline_process1

assign add_signext_12 = sumdelay_pipeline1[0];
  assign add_signext_13 = sumdelay_pipeline1[1];
  assign add_temp_6 = add_signext_12 + add_signext_13;
  assign sum2 = add_temp_6[34:0];

always @ ( posedge clk_50m)
 begin: Finalsum_reg_process
 if (rst_n == 1'b0) begin
 acc_final <= 0;
 end
 else begin
 if (cur_count == 4'b1110) begin
 acc_final <= sum2;
 end
 end
 end // Finalsum_reg_process

// Assignment Statements
  assign filter_out = acc_final;

always @(posedge clk_50m) begin
 if (rst_n == 1'b0) begin
 data_ready <= 1'b0;
 end
 else if (cur_count == 4'b1110) begin
 data_ready <= 1'b1;
 end else begin
 data_ready <= 1'b0;
 end
 end
endmodule // filter_detector
```

例化两个相同的滤波器模块，对两路信号同时进行滤波。由于滤波器结构完全相同且时钟同步，使用其中一路的计算完成输出信号即可。此外，由公式可知滤波后幅值衰减至原信号的一半，需要将输出结果左移一位以补偿。

```verilog
module filter (
    input clk_50m,
    input rst_n,

input [15:0] sin_mixed,
    input [15:0] cos_mixed,
    input        data_valid,

output wire [15:0] sin,
    output wire [15:0] cos,
    output wire        data_ready
);

wire [34:0] sin_raw;
    wire [34:0] cos_raw;

assign sin        = sin_raw[33:18];
    assign cos        = cos_raw[33:18];

filter_detector sin_filter_detector (
        .clk_50m   (clk_50m),
        .clk_enable(1'b1),
        .data_valid(data_valid),
        .rst_n     (rst_n),
        .filter_in (sin_mixed),
        .filter_out(sin_raw),
        .data_ready(data_ready)
    );

filter_detector cos_filter_detector (
        .clk_50m   (clk_50m),
        .clk_enable(1'b1),
        .data_valid(data_valid),
        .rst_n     (rst_n),
        .filter_in (cos_mixed),
        .filter_out(cos_raw),
        .data_ready()
    );

endmodule
```

### 测试

将两个部分组合在一起实现完整的检波器。
```verilog
module detector (
    input clk_50m,
    input rst_n,

input [15:0] sync_carrier,
    input [15:0] ch_sin,
    input [15:0] ch_cos,
    input        data_valid,

output wire [15:0] sin,
    output wire [15:0] cos,
    output wire        data_ready
);

wire [15:0] sin_mixed;
    wire [15:0] cos_mixed;
    wire        mixer_data_ready;

mixer u_mixer (
        .clk_50m     (clk_50m),
        .rst_n       (rst_n),
        .sync_carrier(sync_carrier),
        .ch_sin      (ch_sin),
        .ch_cos      (ch_cos),
        .data_valid  (data_valid),
        .sin_mixed   (sin_mixed),
        .cos_mixed   (cos_mixed),
        .data_ready  (mixer_data_ready)
    );

filter u_filter (
        .clk_50m   (clk_50m),
        .rst_n     (rst_n),
        .sin_mixed (sin_mixed),
        .cos_mixed (cos_mixed),
        .data_valid(mixer_data_ready),
        .sin       (sin),
        .cos       (cos),
        .data_ready(data_ready)
    );

endmodule
```

测试激励如下，输入生成的激磁信号及正余弦调制信号，输出为正余弦包络。

```verilog
`timescale 1 ns / 1 ns
module detector_tb;

localparam N = 2000;

reg clk_50m = 0, rst_n = 0, data_valid = 0;
    wire data_ready;
    wire [15:0] sin, cos;
    reg [15:0] sync_carrier = 0, ch_sin = 0, ch_cos = 0;
    reg     [15:0] data_sin    [N - 1:0];
    reg     [15:0] data_cos    [N - 1:0];
    reg     [15:0] data_carrier[N - 1:0];
    integer        i = 0;

initial begin
 $readmemh("../../matlab/sin.txt", data_sin);
 $readmemh("../../matlab/cos.txt", data_cos);
 $readmemh("../../matlab/carrier.txt", data_carrier);
 #30 rst_n <= 1;
 #30000000 $stop;
 end

always begin
 #10 clk_50m <= ~clk_50m;
 end

GTP_GRS GRS_INST (.GRS_N(rst_n));

always begin
        #4970;

ch_sin = data_sin;
 ch_cos = data_cos;
 sync_carrier = data_carrier;

if (i == N - 1) begin
            i = 0;
        end else begin
            i = i + 1;
        end
        data_valid = 1;
        #30;
        data_valid = 0;
    end

detector u_detector (
        .clk_50m     (clk_50m),
        .rst_n       (rst_n),
        .sync_carrier(sync_carrier),
        .ch_sin      (ch_sin),
        .ch_cos      (ch_cos),
        .data_valid  (data_valid),
        .sin         (sin),
        .cos         (cos),
        .data_ready  (data_ready)
    );

endmodule
```

生成波形的Matlab程序如下：

```matlab
N = 2000;
n = 0:N-1;
x = fix((2^15 - 1) * sin(2*pi*n/N) .* sin(100*2*pi*n/N));
y = fix((2^15 - 1) * cos(2*pi*n/N) .* sin(100*2*pi*n/N));
z = fix((2^15 - 1) * sin(100*2*pi*n/N));

fid1 = fopen('sin.txt','wt');
fid2 = fopen('cos.txt','wt');
fid3 = fopen('carrier.txt','wt');

for i = 1:N
    fprintf(fid1,'%s\n',dec2hex(x(i),4));
    fprintf(fid2,'%s\n',dec2hex(y(i),4));
    fprintf(fid3,'%s\n',dec2hex(z(i),4));
end

fclose(fid1);
fclose(fid2);
fclose(fid3);
```

仿真结果正确，观察到两路正余弦包络输出。

本帖最后由 Jimmy_Arareb 于 2023-1-25 23:21 编辑