[求助] 请大佬讲解,我想实现点击按键后相位发生特定突变的效果,为什么我写的代码无实现

崇博诚   2025-6-15 23:04 楼主
悬赏 5 分 芯积分未解决

我每次点击按键cnt有反应会加1,但是决定相位的变量rom_addr没有反应

`timescale 1ns / 1ps

module top
(
	input                            sclk   ,
	input                            srst_n ,
	
	//锟斤拷一路ADC
    input   [9:0]  ad_data_1  ,  //锟斤拷一路ADC锟斤拷锟斤拷
    input          ad_otr_1   ,  //锟斤拷一路ADC锟斤拷锟斤拷锟窖癸拷锟斤拷锟斤拷锟斤拷瘫锟街�
    output         ad_clk_1   ,  //锟斤拷一路ADC锟斤拷锟斤拷时锟斤拷
    output         ad_oe_1    ,  //锟斤拷一路ADC锟斤拷锟绞癸拷锟�
    //锟节讹拷路ADC
    input   [9:0]  ad_data_2  ,  //锟节讹拷路ADC锟斤拷锟斤拷
    input          ad_otr_2   ,  //锟节讹拷路ADC锟斤拷锟斤拷锟窖癸拷锟斤拷锟斤拷锟斤拷瘫锟街�
    output         ad_clk_2   ,  //锟节讹拷路ADC锟斤拷锟斤拷时锟斤拷
    output         ad_oe_2    ,    //锟节讹拷路ADC锟斤拷锟绞癸拷锟�
	
    output[13:0]                     da2_data,                 //DA data 
    output                           da2_clk,                  //DA clock
    output                           da2_wrt,
    
    output[13:0]                     da1_data,                 //DA data 
    output                           da1_clk,                  //DA clock
    output                           da1_wrt,
    
    
	input                            key1_in
	
);


wire dac_clk;
wire da_clk;

clk_120Mhz clk_120Mhz(
.reset(~srst_n),
.clk_in1(sclk),
.clk_out1(dac_clk),
.clk_out2(da_clk),
.locked()
);
assign da2_clk = da_clk;
assign da2_wrt = da_clk;
wire[13:0]                      output_data;     
reg[8:0]                        rom_addr;                //rom address




wire [8:0] rom_addr_shifted;

wire key1value;
key_debounce key01(
    .clk(dac_clk) ,
    .rst_n(srst_n) ,

    .key(key1_in) ,         //澶栭儴杈撳叆鐨勬寜閿��
    .key_value(key1value) ,   //娑堟姈鍚庣殑鎸夐敭鍊�
    .key_flag () ,     //娑堟姈鍚庣殑鎸夐敭鍊肩殑鏁堟爣蹇�
    .choose(),//鏁板瓧鍜屾ā鎷熻В璋冭瘑鍒殑閫夋嫨
    .phaseadd(rom_addr_shifted)
);

localparam [8:0] out_putphase = 9'd100;


reg [8:0] cnt;             // 璁℃暟鍙橀噺锛屾瘡娆′粠1鍙�0鏃跺姞1
reg keyvalue_prev;         // 璁板綍涓婁竴涓椂閽熷懆鏈熺殑 keyvalue 鍊�
always @(posedge dac_clk or negedge srst_n) begin
    if (!srst_n) begin
        keyvalue_prev <= 1'b1;  // 鍒濆鍖栦负1锛岄槻姝㈢涓�娆¤瑙﹀彂
        cnt <= 9'd0;            // 鍒濆璁℃暟涓�0
        rom_addr <= 'd128;
    end else begin
        if (keyvalue_prev && !key1value) begin  // 鎸夐敭涓嬮檷娌�
            cnt <= cnt + 1;
            rom_addr <= rom_addr + out_putphase;
        end 
        else if (rom_addr + 9'd1 > 'd255) rom_addr <= rom_addr + 9'd1 - 'd512; 
        else rom_addr <= rom_addr + 9'd1; 
        keyvalue_prev <= key1value;
    end
end


wire [8:0] outcnt;
assign outcnt = cnt;
wire minus;
assign miuns = key1value-keyvalue_prev;
wire [8:0] addrout;
assign addrout = rom_addr ;


dam_rom da_rom_m0 
(
.clka                           (dac_clk                  ),  
.ena                            (1'b1                     ),     
.addra                          (rom_addr                 ), 
.douta                          (output_data                 )  
);

assign da2_data = output_data;

ila_0 ilaa(
.clk(sclk),
.probe0(da2_data),
.probe1(outcnt),
.probe2(dac_clk),
.probe3(key1value),
.probe4(miuns),
.probe5(addrout)
);
endmodule

 

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