先声明 偶才接触这东西10来天的样子 不怎么熟练 外加这边的人看上去似乎都是专业的= =
最好能给点指导 或者能给个计数器的实例看下 我一般情况下就能搞懂了
以下这段实验用的东西为啥通不过编译呢?
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY test IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
input : IN STD_LOGIC;
output : OUT STD_LOGIC
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END test;
-- Architecture Body
ARCHITECTURE test_architecture OF test IS
BEGIN
output <= input;
END test_architecture;
问题是这样
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
Info: Processing started: Tue Jan 15 17:30:43 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test
Warning: Can't analyze file -- file C:/Documents and Settings/Alucard/My Documents/study/test/block_name.vhd is missing
Info: Found 1 design units, including 1 entities, in source file test.bdf
Info: Found entity 1: test
Warning: Can't analyze file -- file C:/Documents and Settings/Alucard/My Documents/study/test/=1.vhd is missing
Error: Can't compile duplicate declarations of entity "test" into library "work"
Error: Found entity "test" in file test.bdf
Error: Found entity "test" in file test.vhd
Info: Found 2 design units, including 1 entities, in source file test.vhd
Info: Found design unit 1: test-test_architecture
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 2 warnings
Info: Allocated 150 megabytes of memory during processing
Error: Processing ended: Tue Jan 15 17:30:48 2008
Error: Elapsed time: 00:00:05
应该就是如同楼上说的,文件名和实体名要一致
当然你也可以把这个文件设置为顶层文件!
vhdl保存的文件名需要与实体名一致 也就是说你的保存的文件要叫test
block_name.vhd is missing
看看文件的名字
VHDL要求文件名和实体名要一致
你的文件名称应该保存为test
并且想编译通过的话需要将文件置为顶层文件,也就是将现在你编辑的文件激活为当前文件,要不然系统编译的还是上一次的文件