我想转换integer类型的信号为real类型
程序如下。
这段程序在maxplus II报错：
file standard.vhdl:Unsupported feature error:floating is not supported
在quartus II中报错：
Error (10414): VHDL error at yuvtorgb.vhd(22), at object "red": a real cannot be non-constant
程序如下，请教各位大虾：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity yuvtorgb is
port(
RAM_DBUS : in std_logic_vector(7 downto 0);
y2_select : in std_logic;
indata_v : in std_logic_vector(7 downto 0);
indata_y1 : in std_logic_vector(7 downto 0);
indata_u : in std_logic_vector(7 downto 0);
indata_y2 : in std_logic_vector(7 downto 0);
test: out std_logic
);
end entity;
architecture a of yuvtorgb is
signal data_v : INTEGER;
signal data_y1 : INTEGER;
signal data_u : INTEGER;
signal data_y2 : INTEGER;
signal red : real range 0.0 to 1000.0 :=10.0;
signal green : real;
signal blue : real;
signal addred : std_logic_vector(18 downto 0);
signal lcdpixel_num : integer range 0 to 2570;
signal pickup_tmp : std_logic;
begin
test<='1';
data_v<=conv_integer(indata_v);
data_y1<=conv_integer(indata_y1);
data_u<=conv_integer(indata_u);
data_y2<=conv_integer(indata_y2);
process(y2_select)
begin
if(y2_select'event and y2_select='0') then
red<=real(data_y1);
--red=1.164 * (data_y1 - 16) + 1.596 * (data_v - 128);
--green=1.164 * (data_y1 - 16) - 0.813 * (data_v - 128) - 0.392 * (data_u - 128);
--blue=1.164 * (data_y1 - 16) + 2.017 * (data_u - 128);
end if;
end process;
--
end a;
不支持浮点型,如果只是仿真可以用modesim试试看.
我是想把YCrCb解码为RGB，我想用vhdl做（前面的程序都是用vhdl做的），那怎么办？请教各位
硬件 是直接在底层工作的，你要考虑的不光是他的功能，
溢出处理，符号等都要考虑的阿。
光凭公式直接描述 是不可以的，
这个最好在有个图片 来验证 一下。
这才是 逻辑对了。
之后 还有timing，也就是你的做法能跑到多快，用了系统多少资源。
--*******************************************************************
-- Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
-- This text/file contains proprietary, confidential
-- information of Xilinx, Inc., is distributed under license
-- from Xilinx, Inc., and may be used, copied and/or
-- disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you
-- a license to use this text/file solely for design, simulation,
-- implementation and creation of design files limited
-- to Xilinx devices or technologies. Use with non-Xilinx
-- devices or technologies is expressly prohibited and
-- immediately terminates your license unless covered by
-- a separate agreement.
--
-- Xilinx is providing this design, code, or information
-- "as is" solely for use in developing programs and
-- solutions for Xilinx devices. By providing this design,
-- code, or information as one possible implementation of
-- this feature, application or standard, Xilinx is making no
-- representation that this implementation is free from any
-- claims of infringement. You are responsible for
-- obtaining any rights you may require for your implementation.
-- Xilinx expressly disclaims any warranty whatsoever with
-- respect to the adequacy of the implementation, including
-- but not limited to any warranties or representations that this
-- implementation is free from claims of infringement, implied
-- warranties of merchantability or fitness for a particular
-- purpose.
--
-- Xilinx products are not intended for use in life support
-- appliances, devices, or systems. Use in such applications are
-- expressly prohibited.
--
-- This copyright and support notice must be retained as part
-- of this text at all times. (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
-- Title - Xil_YCrCb2RGB.vhd
-- Author(s) - GZ & WCC, Xilinx
-- Creation - 7 Dec 2005
--
-- $RCSfile: Xil_YCrCb2RGB.vhd,v $ $Revision: 1.10 $ $Date: 2006/03/15 19:56:55 $
--
-- Description -
--
--
--
--*******************************************************************
-- ******************************************************************
-- *007* YCrCb2RGB Macro from imagexlib
--
-- Description: Color Space Converter (YCrCb to RGB)
--
-- ******************************************************************
--LIBRARY genxlib;
--USE genxlib.genxlib_utils.ALL;
--
--LIBRARY mathxlib;
--USE mathxlib.mathxlib_utils.ALL;
--
--LIBRARY imagexlib;
--USE imagexlib.imagexlib_utils.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
LIBRARY work;
USE work.color_space_pkg.all;
LIBRARY work;
USE work.genxlib_utils.ALL;
-- ******************************************************************
-- *009* YCrCb2RGB Macro
--
-- Description: Color Space Converter (RGB to YCrCb)
--
-- Generalized conversion:
--
-- R = (Y - Yoffset) + ACoeff' * (Cr - Coffset)
-- G = (Y - Yoffset) + BCoeff' * (Cr - 0.5) + CCoeff' * (Cb - 0.5)
-- B = (Y - Yoffset) + DCoeff' * (Cb - 0.5)
--
-- R = Y + ACoeff' * Cr - Roffset
-- G = Y + BCoeff' * Cr + CCoeff' * Cb - Goffset
-- B = Y + DCoeff' * Cb - Boffset
--
-- In order to complement RGB2YCrCb:
--
-- ACoeff' = 1/CCOEFF
-- BCoeff' = ACOEFF/CCOEFF * (1-ACOEFF-BCOEFF)
-- CCoeff' = BCOEFF/DCOEFF * (1-ACOEFF-BCOEFF)
-- DCoeff' = 1/DCOEFF
-- Roffset = Yoffset + Acoeff' * Coffset
-- Goffset = Yoffset + (Bcoeff' + Ccoeff') * Coffset
-- Boffset = Yoffset + Dcoeff' * Coffset
--
-- ITU 601 (SDTV) standard:
-- if RGB data is between 0 and 255
-- R = Y + 1.40252 * (Cr - 0.5)
-- G = Y - 0.24642 * (Cr - 0.5) - 0.11840 * (Cb - 0.5)
-- B = Y + 1.77305 * (Cb - 0.5)
--
-- In order to better match the RGB2YCbCr module:
-- For R: ACoeff' = (1/CCOEF) value 2048/1460 is approximated instead of 1.40252
-- For B: DCoeff' = (1/DCOEF) value 2048/1155 is approximated instead of 1.77305
--
entity Xil_YCrCb2RGB is
generic (
FAMILY_HAS_MAC: integer:= 1;
FABRIC_ADDS : integer:= 1; -- Adders are implemented using logic fabric based adders
IWIDTH : integer:= 9;
CWIDTH : integer:= 13; -- Coefficients are signed, CWIDTH.CWIDTH-2 format
MWIDTH : integer:= 23; -- ONLY FOR NON-V4: Controls bits witheld after mults.
OWIDTH : integer:= 9; -- OTHERWISE (default) IWIDTH+CWIDTH+1;
RGBMAX : integer:= 255;
RGBMIN : integer:= 0;
ACOEF : integer:= 2872; -- 1.4023 *pow2(CWIDTH-2)
BCOEF : integer:= -1461; -- -0.7133 *pow2(CWIDTH-2)
CCOEF : integer:= -703; -- -0.3434 *pow2(CWIDTH-2)
DCOEF : integer:= 3630; -- 1.7724 *pow2(CWIDTH-2)
ROFFSET : integer:= -366592; -- Should be MWIDTH bits wide
GOFFSET : integer:= 278016;
BOFFSET : integer:= -463616;
HAS_CLIP : integer:= 1;
HAS_CLAMP : integer:= 1);
port (
Y : in std_logic_vector(IWIDTH-1 downto 0); -- Y = a(R-G) + G + b(B-G)
Cr : in std_logic_vector(IWIDTH-1 downto 0); -- Cr = d(R-Y)
Cb : in std_logic_vector(IWIDTH-1 downto 0); -- Cb = c(B-Y)
R : out std_logic_vector(OWIDTH-1 downto 0);
G : out std_logic_vector(OWIDTH-1 downto 0);
B : out std_logic_vector(OWIDTH-1 downto 0);
V_SYNC_in : in std_logic := '0';
H_SYNC_in : in std_logic := '0';
PIX_EN_in : in std_logic := '1';
V_SYNC_out : out std_logic;
H_SYNC_out : out std_logic;
PIX_EN_out : out std_logic;
clk : in std_logic;
ce : in std_logic := '1';
sclr : in std_logic := '0');
end Xil_YCrCb2RGB;
architecture rtl of Xil_YCrCb2RGB is
-- High level constants
constant MODULE_LATENCY : integer := YCrCb2RGB_LATENCY(FAMILY_HAS_MAC, FABRIC_ADDS, HAS_CLIP, HAS_CLAMP); -- ADDER_DELAY is set to 1, MULT_DELAY is 2
constant ACOEFvec : std_logic_vector(CWIDTH-1 downto 0) := conv_std_logic_vector(ACOEF, CWIDTH); -- ACOEF SRL ACOEFF_RANGE, CWIDTH); -- ACOEFF constant is normalized
constant BCOEFvec : std_logic_vector(CWIDTH-1 downto 0) := conv_std_logic_vector(BCOEF, CWIDTH); -- BCOEF SRL BCOEFF_RANGE, CWIDTH); -- BCOEFF constant is normalized
constant CCOEFvec : std_logic_vector(CWIDTH-1 downto 0) := conv_std_logic_vector(CCOEF,CWIDTH);
constant DCOEFvec : std_logic_vector(CWIDTH-1 downto 0) := conv_std_logic_vector(DCOEF,CWIDTH);
constant Goffsetvec : std_logic_vector(MWIDTH-1 downto 0) := conv_std_logic_vector(GOFFSET,MWIDTH);
constant Roffsetvec : std_logic_vector(MWIDTH-1 downto 0) := conv_std_logic_vector(ROFFSET,MWIDTH);
constant Boffsetvec : std_logic_vector(MWIDTH-1 downto 0) := conv_std_logic_vector(BOFFSET,MWIDTH);
constant MAXvec : std_logic_vector(OWIDTH+1 downto 0) := conv_std_logic_vector(RGBMAX,OWIDTH+2);
constant MINvec : std_logic_vector(OWIDTH+1 downto 0) := conv_std_logic_vector(RGBMIN,OWIDTH+2);
-- This is the delay of a virtex4 multiplier followed by a rounder. In order to facilitate
-- grouping the rounder with the mult into the same DSP48, overall latency must be 2
-- Low level constants
constant logic0 : std_logic := '0';
constant logic1 : std_logic := '1';
-- signal declarations
signal Cr_delay : std_logic_vector(IWIDTH downto 0);
signal Cb_delay : std_logic_vector(IWIDTH downto 0);
signal Cb_unsign : std_logic_vector(IWIDTH downto 0);
signal Y_delay : std_logic_vector(IWIDTH-1 downto 0);
signal Y_padded : std_logic_vector(OWIDTH downto 0);
signal Acoef_by_Cr : std_logic_vector(IWIDTH+CWIDTH downto 0);
signal Bcoef_by_Cr : std_logic_vector(IWIDTH+CWIDTH downto 0);
signal Ccoef_by_Cb : std_logic_vector(IWIDTH+CWIDTH downto 0);
signal Dcoef_by_Cb : std_logic_vector(IWIDTH+CWIDTH downto 0);
signal Acoef_by_Cr_rnd : std_logic_vector(MWIDTH downto 0);
signal Bcoef_by_Cr_rnd : std_logic_vector(MWIDTH downto 0);
signal Ccoef_by_Cb_rnd : std_logic_vector(MWIDTH downto 0);
signal Dcoef_by_Cb_rnd : std_logic_vector(MWIDTH downto 0);
signal G_int : std_logic_vector(OWIDTH+1 downto 0);
signal B_int : std_logic_vector(OWIDTH+1 downto 0);
signal R_int : std_logic_vector(OWIDTH+1 downto 0);
signal G_postmax : std_logic_vector(OWIDTH+1 downto 0);
signal B_postmax : std_logic_vector(OWIDTH+1 downto 0);
signal R_postmax : std_logic_vector(OWIDTH+1 downto 0);
signal G_postmin : std_logic_vector(OWIDTH+1 downto 0);
signal B_postmin : std_logic_vector(OWIDTH+1 downto 0);
signal R_postmin : std_logic_vector(OWIDTH+1 downto 0);
signal sync_in : std_logic_vector(2 downto 0);
signal sync_out : std_logic_vector(2 downto 0);
begin
---------------------------------------------------------------------
-- Generate the output sync signals
---------------------------------------------------------------------
SYNC_in(2) <= PIX_EN_in;
SYNC_in(1) <= V_SYNC_in;
SYNC_in(0) <= H_SYNC_in;
del_SYNC : entity work.delay(rtl)
generic map (
width => 3,
delay => MODULE_LATENCY )
port map (
clk => clk,
d => SYNC_in,
q => SYNC_out,
ce => ce);
PIX_EN_out <= SYNC_out(2);
V_SYNC_out <= SYNC_out(1);
H_SYNC_out <= SYNC_out(0);
--------------------------------------------------------------------
-- Create and round Cb*BCOEFF, Cb*DCOEFF, Cr*ACOEFF, Cr*CCOEFF
--------------------------------------------------------------------
del_Cr : entity work.delay(rtl) -- Delay Cr, so Acoef_by_Cr arrives in sync
generic map ( -- with Ccoef_by_Cb to the adder/rounder
width => IWIDTH,
delay => 1)
port map (
clk => clk,
d => Cr,
q => Cr_delay(IWIDTH-1 downto 0),
ce => ce);
del_Cb : entity work.delay(rtl) -- Delay Cb, so Dcoef_by_Cb arrives in sync
generic map ( -- with B_int and G_int are in sync.
width => IWIDTH,
delay => 1)
port map (
clk => clk,
d => Cb,
q => Cb_delay(IWIDTH-1 downto 0),
ce => ce);
Cb_unsign(IWIDTH-1 downto 0) <= Cb;
Cb_unsign(IWIDTH) <= '0'; -- Making sure that Cb and Cr signals are
Cb_delay(IWIDTH) <= '0'; -- interpreted as unsigned
Cr_delay(IWIDTH) <= '0'; -- at the mutlipliers
sp3_v2_v2p: if (FAMILY_HAS_MAC=0) generate
mult_aCr: entity work.mult(rtl) -- ACOEFF * Cr
generic map (
IWIDTHA => IWIDTH+1,
IWIDTHB => CWIDTH)
port map (
clk => clk,
ce => ce,
sclr => sclr,
a => Cr_delay,
b => ACOEFvec,
p => Acoef_by_Cr);
mult_bCr: entity work.mult(rtl) -- BCOEFF * Cr
generic map (
IWIDTHA => IWIDTH+1,
IWIDTHB => CWIDTH)
port map (
clk => clk,
ce => ce,
sclr => sclr,
a => Cr_delay,
b => BCOEFvec,
p => Bcoef_by_Cr);
mult_cCb: entity work.mult(rtl) -- CCOEFF * Cb
generic map (
IWIDTHA => IWIDTH+1,
IWIDTHB => CWIDTH)
port map (
clk => clk,
ce => ce,
sclr => sclr,
a => Cb_unsign,
b => CCOEFvec,
p => Ccoef_by_Cb);
mult_dCb: entity work.mult(rtl) -- DCOEFF * Cb
generic map (
IWIDTHA => IWIDTH+1,
IWIDTHB => CWIDTH)
port map (
clk => clk,
ce => ce,
sclr => sclr,
a => Cb_delay,
b => DCOEFvec,
p => Dcoef_by_Cb);
round_aCr : entity work.radd_sub_sclr(rtl) -- Rounding and offset compensating R with one adder
generic map (
width => MWIDTH,
add => true,
fabric=> 1)
port map (
a => Acoef_by_Cr(IWIDTH+CWIDTH-1 downto IWIDTH+CWIDTH-MWIDTH),
b => Roffsetvec,
s => Acoef_by_Cr_rnd,
c_in => logic0,
clk => clk,
ce => ce,
sclr => sclr);
round_bCr : entity work.radd_sub_sclr(rtl) -- Adding and Rounding of Ccoef_by_Cr and Bcoef_by_Cb_rnd using one adder
generic map (
width => MWIDTH,
add => true,
fabric=> 1)
port map (
a => Bcoef_by_Cr(IWIDTH+CWIDTH-1 downto IWIDTH+CWIDTH-MWIDTH),
b => Ccoef_by_Cb_rnd(MWIDTH-1 downto 0),
s => Bcoef_by_Cr_rnd,
c_in => logic0,
clk => clk,
ce => ce,
sclr => sclr);
round_cCb : entity work.radd_sub_sclr(rtl) -- Rounding and offset compensating G with one adder
generic map (
width => MWIDTH,
add => true,
fabric=> 1)
port map (
a => Ccoef_by_Cb(IWIDTH+CWIDTH-1 downto IWIDTH+CWIDTH-MWIDTH),
b => Goffsetvec,
s => Ccoef_by_Cb_rnd,
c_in => logic0,
clk => clk,
ce => ce,
sclr => sclr);
round_dCb : entity work.radd_sub_sclr(rtl) -- Rounding and offset compensating G with one adder
generic map (
width => MWIDTH,
add => true,
fabric=> 1)
port map (
a => Dcoef_by_Cb(IWIDTH+CWIDTH-1 downto IWIDTH+CWIDTH-MWIDTH),
b => Boffsetvec,
s => Dcoef_by_Cb_rnd,
c_in => logic0,
clk => clk,
ce => ce,
sclr => sclr);
end generate;
v4: if (FAMILY_HAS_MAC = 1) generate -- DSP48 based implementation
mult_aCr: entity work.mac(rtl) -- ACOEFF * Cr + Roffsetvec
generic map ( -- offset contains rounding const
IWIDTHA => IWIDTH+1,
IWIDTHB => CWIDTH,
OWIDTH => MWIDTH,
ROUND_MODE=> 0,
HAS_C => 1)
port map (
clk => clk,
ce => ce,
sclr => sclr,
a => Cr_delay,
b => ACOEFvec,
c => Roffsetvec,
p => Acoef_by_Cr_rnd(MWIDTH downto 1));
-- sign extension for simulation (v4 results are the same as s3_v2_v2p)
--Acoef_by_Cr_rnd(IWIDTH+CWIDTH) <= Acoef_by_Cr_rnd(IWIDTH+CWIDTH-1);
mult_BCr: entity work.mac(rtl) -- BCOEFF * Cr + CCOEFF * Cb + Goffsetvec
generic map (
IWIDTHA => IWIDTH+1,
IWIDTHB => CWIDTH,
OWIDTH => MWIDTH,
ROUND_MODE=> 0,
CREG => 0, -- use Pcascade chain
HAS_C => 1)
port map (
clk => clk,
ce => ce,
sclr => sclr,
a => Cr_delay,
b => BCOEFvec,
c => Ccoef_by_Cb_rnd(MWIDTH downto 1),
p => Bcoef_by_Cr_rnd(MWIDTH downto 1));
-- sign extension for simulation (v4 results are the same as s3_v2_v2p)
--Bcoef_by_Cr_rnd(IWIDTH+CWIDTH) <= Bcoef_by_Cr_rnd(IWIDTH+CWIDTH-1);
mult_cCb: entity work.mac(rtl) -- CCOEFF * Cb + Goffsetvec
generic map ( -- offset contains rounding const
IWIDTHA => IWIDTH+1,
IWIDTHB => CWIDTH,
OWIDTH => MWIDTH,
ROUND_MODE=> 0,
HAS_C => 1)
port map (
clk => clk,
ce => ce,
sclr => sclr,
a => Cb_unsign,
b => CCOEFvec,
c => Goffsetvec,
p => Ccoef_by_Cb_rnd(MWIDTH downto 1));
-- sign extension for simulation (v4 results are the same as s3_v2_v2p)
-- Ccoef_by_Cb_rnd(IWIDTH+CWIDTH) <= Ccoef_by_Cb_rnd(IWIDTH+CWIDTH-1);
mult_DCb: entity work.mac(rtl) -- DCOEFF * Cb + Boffsetvec
generic map ( -- offset contains rounding const
IWIDTHA => IWIDTH+1,
IWIDTHB => CWIDTH,
OWIDTH => MWIDTH,
ROUND_MODE=> 0,
HAS_C => 1)
port map (
clk => clk,
ce => ce,
sclr => sclr,
a => Cb_delay,
b => DCOEFvec,
c => Boffsetvec,
p => Dcoef_by_Cb_rnd(MWIDTH downto 1));
-- sign extension for simulation (v4 results are the same as s3_v2_v2p)
--Dcoef_by_Cb_rnd(IWIDTH+CWIDTH) <= Dcoef_by_Cb_rnd(IWIDTH+CWIDTH-1);
-- Acoef_by_Cr_rnd(MWIDTH) <= Acoef_by_Cr_rnd(MWIDTH-1);
-- Bcoef_by_Cr_rnd(MWIDTH) <= Bcoef_by_Cr_rnd(MWIDTH-1);
-- Ccoef_by_Cb_rnd(MWIDTH) <= Ccoef_by_Cb_rnd(MWIDTH-1);
-- Dcoef_by_Cb_rnd(MWIDTH) <= Dcoef_by_Cb_rnd(MWIDTH-1);
Acoef_by_Cr_rnd(0) <= '0';
Bcoef_by_Cr_rnd(0) <= '0';
Ccoef_by_Cb_rnd(0) <= '0';
Dcoef_by_Cb_rnd(0) <= '0';
end generate;
--------------------------------------------------------------------
-- Add Y component
--------------------------------------------------------------------
del_Y : entity work.delay(rtl) -- Delay matching: y is delayed so it can be combined with rounded signals
generic map (
width => IWIDTH,
delay => 4) -- 3+FAMILY_HAS_MAC -- ADD_DELAY(FAMILY_HAS_MAC, FABRIC_ADDS)+MULT_DELAY(FAMILY_HAS_MAC)
port map (
clk => clk,
d => Y,
q => y_delay,
ce => ce);
connect_Y: if (IWIDTH=OWIDTH) generate
Y_padded(IWIDTH-1 downto 0) <= y_delay;
end generate;
padd_Y: if (IWIDTH
Y_padded(OWIDTH-1 downto OWIDTH-IWIDTH) <= y_delay;
Y_padded(OWIDTH-IWIDTH-1 downto 0) <= (others => '0');
end generate;
truncate_Y: if (IWIDTH>OWIDTH) generate
Y_padded(OWIDTH-1 downto 0) <= y_delay(IWIDTH-1 downto IWIDTH-OWIDTH);
end generate;
Y_padded(OWIDTH) <= '0'; -- Makes sure Y_padded is unsigned positive
add_R : entity work.radd_sub_sclr(rtl)
generic map (
width => OWIDTH+1,
add => true,
a_signed => true,
b_signed => false,
delay => 2-FABRIC_ADDS,
fabric => FABRIC_ADDS)
port map (
clk => clk,
a => Acoef_by_Cr_rnd(MWIDTH-2 downto MWIDTH-OWIDTH-2),
b => Y_padded,
s => R_int,
c_in => logic0,
ce => ce,
sclr => sclr);
add_G : entity work.radd_sub_sclr(rtl) --
generic map (
width => OWIDTH+1,
add => true,
a_signed => true,
b_signed => false,
delay => 2-FABRIC_ADDS,
fabric => FABRIC_ADDS)
port map (
clk => clk,
a => Bcoef_by_Cr_rnd(MWIDTH-2 downto MWIDTH-OWIDTH-2),
b => Y_padded,
s => G_int,
c_in => logic0,
ce => ce,
sclr => sclr);
add_B : entity work.radd_sub_sclr(rtl) --
generic map (
width => OWIDTH+1,
add => true,
a_signed => true,
b_signed => false,
delay => 2-FABRIC_ADDS,
fabric => FABRIC_ADDS)
port map (
clk => clk,
a => Dcoef_by_Cb_rnd(MWIDTH-2 downto MWIDTH-OWIDTH-2),
b => Y_padded,
s => B_int,
c_in => logic0,
ce => ce,
sclr => sclr);
-----------------------------------------------------
-- clipping and clamping of R,G,B
-----------------------------------------------------
clip: if (HAS_CLIP=1) generate
max_R : entity work.max_sat(rtl) -- Add the logic to catch overflow saturation (max)
generic map (width => OWIDTH+2)
port map (
a => R_int,
max => MAXvec,
ma => R_postmax,
clk => clk,
ce => ce,
sclr => sclr);
max_G : entity work.max_sat(rtl) -- Add the logic to catch overflow saturation (max)
generic map (width => OWIDTH+2)
port map (
a => G_int,
max => MAXvec,
ma => G_postmax,
clk => clk,
ce => ce,
sclr => sclr);
max_B : entity work.max_sat(rtl) -- Add the logic to catch overflow saturation (max)
generic map (width => OWIDTH+2)
port map (
a => B_int,
max => MAXvec,
ma => B_postmax,
clk => clk,
ce => ce,
sclr => sclr);
end generate;
no_clip: if (HAS_CLIP/=1) generate
R_postmax <= R_int;
G_postmax <= G_int;
B_postmax <= B_int;
end generate;
clamp: if (HAS_CLAMP=1) generate
min_R : entity work.min_sat(rtl) -- Add the logic to catch underflow saturation (min)
generic map (width => OWIDTH+2)
port map (
a => R_postmax,
min => MINvec,
ma => R_postmin,
clk => clk,
ce => ce,
sclr => sclr);
min_G : entity work.min_sat(rtl) -- Add the logic to catch underflow saturation (min)
generic map (width => OWIDTH+2)
port map (
a => G_postmax,
min => MINvec,
ma => G_postmin,
clk => clk,
ce => ce,
sclr => sclr);
min_B : entity work.min_sat(rtl) -- Add the logic to catch underflow saturation (min)
generic map (width => OWIDTH+2)
port map (
a => B_postmax,
min => MINvec,
ma => B_postmin,
clk => clk,
ce => ce,
sclr => sclr);
end generate;
no_clamp: if (HAS_CLAMP/=1) generate
R_postmin <= R_postmax;
G_postmin <= G_postmax;
B_postmin <= B_postmax;
end generate;
R <= R_postmin(OWIDTH-1 downto 0);
G <= G_postmin(OWIDTH-1 downto 0);
B <= B_postmin(OWIDTH-1 downto 0);
end rtl;
ACOEF : integer:= 2872; -- 1.4023 *pow2(CWIDTH-2)
BCOEF : integer:= -1461; -- -0.7133 *pow2(CWIDTH-2)
CCOEF : integer:= -703; -- -0.3434 *pow2(CWIDTH-2)
DCOEF : integer:= 3630; -- 1.7724 *pow2(CWIDTH-2)
ROFFSET : integer:= -366592; -- Should be MWIDTH bits wide
这些怎么理解？
为什么1.4023 对应2872？
...是不是应该加上些标注阿，不然怎么看的懂...
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