library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity read_write is
port( clk : in std_logic ;
mcu_oe : in std_logic;
mcu_we : in std_logic;
mcu_data : inout std_logic_vector(7 downto 0);
);
end ;
architecture sram of read_write is
begin
PROCESS(clk,mcu_oe,mcu_we)
BEGIN
IF clk = '1' THEN
IF mcu_oe = '0' THEN -- 单片机从SRAM读取书据
mcu_data <= sram_data;
ELSE
mcu_data <= "ZZZZZZZZ" ; --空闲时数据线为高阻态
END IF;
IF mcu_we='0' THEN -- 单片机将数据写入SRAM
sram_data <=mcu_data;
ELSE
sram_data<= "ZZZZZZZZ" ;
END IF;
END IF;
ELSE
sram_data <= "ZZZZZZZZ" ;
END IF ;
END;
END;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity read_write is
port( clk : in std_logic ;
mcu_oe : in std_logic;
mcu_we : in std_logic;
mcu_data : inout std_logic_vector(7 downto 0);
);
end ;
architecture sram of read_write is
begin
PROCESS(clk,mcu_oe,mcu_we)
BEGIN
IF clk = '1' THEN
IF mcu_oe = '0' THEN -- 单片机从SRAM读取书据
mcu_data <= sram_data;
ELSE
mcu_data <= "ZZZZZZZZ" ; --空闲时数据线为高阻态
END IF;
IF mcu_we='0' THEN -- 单片机将数据写入SRAM
sram_data <=mcu_data;
ELSE
sram_data<= "ZZZZZZZZ" ;
END IF;
ELSE
sram_data <= "ZZZZZZZZ" ;
END IF ;
END;
END;
挺有意思的,单片机控制CPLD?CPLD自己就是一个IC了,可以自己独立工作的,为什么还用控制啊?