-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program ******
-- Subscription Agreement, Altera MegaCore Function ******
-- Agreement, or other applicable ****** agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to
-- suit user's needs .Comments are provided in each section to help the user
-- fill out necessary details.
-- ***************************************************************************
-- Generated on "06/30/2006 11:18:26"
-- Vhdl Test Bench template for design : diohs_task_logic
--
-- Simulation tool : ModelSim (VHDL)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_textio.all;
USE std.textio.all;
ENTITY diohs_task_logic_tb IS
END diohs_task_logic_tb;
ARCHITECTURE diohs_task_logic_arch OF diohs_task_logic_tb IS
-- constants
-- signals
SIGNAL t_sig_HSIN : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL t_sig_clk : STD_LOGIC:='0';
SIGNAL t_sig_rstn : STD_LOGIC;
SIGNAL t_sig_hs_in : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL t_sig_pwm_ena_highs : STD_LOGIC;
CONSTANT ClockPeriod: Time := 10ns;
FILE results: TEXT is OUT "results.txt";
COMPONENT diohs_task_logic
PORT (
HSIN : in STD_LOGIC_VECTOR(7 downto 0);
clk : in STD_LOGIC;
rstn : in STD_LOGIC;
hs_in : out STD_LOGIC_VECTOR(7 downto 0);
pwm_ena_highs : out STD_LOGIC );
END COMPONENT;
BEGIN
tb : diohs_task_logic PORT MAP (
-- list connections between master ports and signals
HSIN => t_sig_HSIN,
clk => t_sig_clk,
rstn => t_sig_rstn,
hs_in => t_sig_hs_in,
pwm_ena_highs => t_sig_pwm_ena_highs
);
init : PROCESS
-- variable declarations
BEGIN
-- code that executes only once
t_sig_rstn <='0';
wait for 20 ns;
t_sig_rstn <='1';
WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
t_sig_clk <= '1';
wait for 20 ns;
loop
-- t_sig_clk <= transport'0';
-- wait for 5 ns;
-- t_sig_clk <= transport'1';
-- wait for 5 ns;
wait for (ClockPeriod/2);
t_sig_clk <= not t_sig_clk;
end loop;
END PROCESS always;
PROCESS
variable l : line;
variable good_number: boolean;
variable r: std_logic_vector(7 downto 0);
file vector_file: text is in "values.txt";
begin
wait for 20 ns;
while not endfile(vector_file) loop
readline(vector_file,l);
read(l,r,good => good_number);
t_sig_HSIN <= r;
wait for 1000 ns;
end loop;
wait for 200 ns;
assert false
report
"End of simulation"
severity error;
END PROCESS;
process
constant myw: width:= 8;
constant mys: side:= right;
variable wl: line;
begin
wait for 30 ns;
loop
wait for 1000 ns;
writeline(results,wl);
write(wl,t_sig_hs_in,mys,myw);
end loop;
end process;
END diohs_task_logic_arch;
用到了TEXTIO包里的 read/readline, 和write/writeline
源程序：
------------------------------------------------------------------------
-- Library
------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------
-- entity
------------------------------------------------------------------------
entity diohs_task_logic is
port
(
clk: in std_logic;
rstn: in std_logic;
HSIN: in std_logic_vector(7 downto 0);
hs_in: out std_logic_vector(7 downto 0);
pwm_ena_highs: out std_logic
);
end diohs_task_logic;
-------------------------------------------------------------------------
-- architecture
-------------------------------------------------------------------------
architecture arch of diohs_task_logic is
-------------------------------------------------------------------------
-- signal
-------------------------------------------------------------------------
signal HSIN_reg: std_logic_vector(7 downto 0);
signal HSIN_debcnt: std_logic_vector(7 downto 0);
-------------------------------------------------------------------------
begin
-------------------------------------------------------------------------
-- Process: high speed inputs debounce counter;
-------------------------------------------------------------------------
process(rstn,clk,HSIN,HSIN_debcnt,HSIN_Reg)
begin
if rstn='0' then
HSIN_debcnt<=(others => '0');
HSIN_Reg <= (others => '0');
elsif rising_edge(clk) then
if HSIN_debcnt = 99 then
HSIN_debcnt<=(others => '0');
HSIN_Reg <= HSIN;
else
HSIN_debcnt <= HSIN_debcnt + 1;
HSIN_Reg <= HSIN_Reg;
end if;
end if;
end process;
hs_in <= HSIN_Reg;
pwm_ena_highs <= not(HSIN_Reg(2) or HSIN_Reg(1) or HSIN_Reg(0));
end arch
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