[求助] 帮忙看下吧，仿真有误

reg ChZFilt;
reg [5:0] ChZBuf;

assign LineOrigin = ChZFilt;

always @ ( posedge Clk4MHz or negedge Reset_ )
begin
if ( !Reset_ )
begin
ChZBuf <= 6'h00;
ChZFilt <= LO;
end
else
begin
ChZBuf <= ChZBuf << 1;
ChZBuf[0] <= ChZ;
if ( ChZBuf[5:1] == 5'b11111 )
ChZFilt <= HI;
else if ( ChZBuf[5:1] == 5'b00000 )
ChZFilt <= LO;
else
ChZFilt <= ChZFilt;
end
end