usbdemo代码在flash可以运行,无法在ram里面运行?(问题已经解决)
IAR EWARM 4.41 & JLink & STR912FW44 & Windows 2003
我把中断向量表复制到ram的最高端, 一共64bytes.
在flash里面, 中断都没有问题. 但是在ram里面不正常.
我测试了0x04000000 0x50000000 两个开始地址都不行.
谢谢!
91x_vect.s 中的改动:
//*******************************************************************************
// Import the __program_start address from 91x_init.s
//*******************************************************************************
IMPORT __program_start
//*******************************************************************************
// Import exception handlers
//*******************************************************************************
IMPORT Undefined_Handler
IMPORT SWI_Handler
IMPORT Prefetch_Handler
IMPORT Abort_Handler
IMPORT FIQ_Handler
PUBLIC CopyStart
PUBLIC CopyEnd
//*******************************************************************************
// Exception vectors at Boot Flash 0x00000000
//*******************************************************************************
LDR PC, Reset_Addr // @0x00000000
LDR PC, Undefined_Addr // @0x00000004
LDR PC, SWI_Addr // @0x00000008
LDR PC, Prefetch_Addr // @0x0000000C
LDR PC, Abort_Addr // @0x00000010
LDR PC, Reserve_Addr // @0x00000014
LDR PC, IRQ_Addr // @0x00000018
LDR PC, FIQ_Addr // @0x0000001C
Reset_Addr DCD __program_start // @0x00000020
Undefined_Addr DCD 0x50017FC4 // @0x00000024
SWI_Addr DCD 0x50017FC8 // @0x00000028
Prefetch_Addr DCD 0x50017FCC // @0x0000002C
Abort_Addr DCD 0x50017FD0 // @0x00000030
Reserve_Addr DCD 0x50017FD4 // @0x00000034
IRQ_Addr DCD 0x50017FD8 // @0x00000038
FIQ_Addr DCD 0x50017FDC // @0x0000003C
//*******************************************************************************
// Exception vectors at RAM 0x50017FC0 : Copy from 0x00000040 : 64 Bytes
//*******************************************************************************
CopyStart LDR PC, Reset_Addr_RAM // @0x00000040 To 0x50017FC0
LDR PC, Undefined_Addr_RAM // @0x00000044 To 0x50017FC4
LDR PC, SWI_Addr_RAM // @0x00000048 To 0x50017FC8
LDR PC, Prefetch_Addr_RAM // @0x0000004C To 0x50017FCC
LDR PC, Abort_Addr_RAM // @0x00000050 To 0x50017FD0
LDR PC, Reserve_Addr_RAM // @0x00000054 To 0x50017FD4
LDR PC, IRQ_Addr_RAM // @0x00000058 To 0x50017FD8
LDR PC, FIQ_Addr_RAM // @0x0000005C To 0x50017FDC
Reset_Addr_RAM DCD __program_start // @0x00000060 To 0x50017FE0
Undefined_Addr_RAM DCD UndefinedHandler // @0x00000064 To 0x50017FE4
SWI_Addr_RAM DCD SWIHandler // @0x00000068 To 0x50017FE8
Prefetch_Addr_RAM DCD PrefetchAbortHandler // @0x0000006C To 0x50017FEC
Abort_Addr_RAM DCD DataAbortHandler // @0x00000070 To 0x50017FF0
Reserve_Addr_RAM DCD __program_start // @0x00000074 To 0x50017FF4
IRQ_Addr_RAM DCD IRQHandler // @0x00000078 To 0x50017FF8
FIQ_Addr_RAM DCD FIQHandler // @0x0000007C To 0x50017FFC
CopyEnd
//*******************************************************************************
//* Function Name : FIQHandler
//* Description : This function is called when FIQ exception is entered.
//* Input : none
//* Output : none
//*******************************************************************************
91x_init.s 中的改动:
// --- Enable 96K RAM
LDR R0, = SCRO_AHB_UNB
LDR R1, = 0x0191 // PFQBC enabled / DTCM & AHB wait-states disabled
STR R1, [R0]
//*******************************************************************************
// --- Copy Interrupt Vector Table to RAM : 64 bytes 0x04017FC0..0x04017FFF
//*******************************************************************************
LDR R0, =CopyStart
;LDR R1, =0x04017FC0
LDR R1, =0x50017FC0
LDMIA R0!, {R4-R11}
STMIA R1!, {R4-R11}
LDMIA R0!, {R4-R11}
STMIA R1!, {R4-R11}
// --- Initialize Stack pointer registers
// ---Enter each mode in turn and set up the stack pointer
MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit // No interrupts
LDR SP, =SFE(FIQ_STACK) & 0xFFFFFFF8
MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit // No interrupts
附上整个工程文件
可以选择DebugInB0, 在flash调试, 运行正常.
如果选择DebugInRam, 在ram调试, 就无法通过枚举了.
相关链接:
https://bbs.eeworld.com.cn/upfiles/img/20071/2007115162852849.rar
为了在RAM调试, 需要先通过jtag使能内部的RAM
调试时先加载这个91x_ram.mac文件:
其中包含了这个设置函数:
execUserPreload()
{
__message "Enable 96KB RAM to download code ...
";
// SCU_CLKCNTR Fmstr = OSC, RCLK = Fmstr, HCLK = RCLK, PCLK = RCLK, BCLK = RCLK/2
__writeMemory32(0x00020002, 0x5C002000, "Memory");
// SCU_PWRMNG Power Mode = Run mode,
__writeMemory32(0x00000000, 0x5C00200C, "Memory");
// SCU_PCGR0 FMI, PQFBC, SRAM, SRAM_ARBITER, EMI, EXT_MEM_CLK clk enable
__writeMemory32(0x000000DB, 0x5C002014, "Memory");
// SCU_PRR0 RST_FMI, RST_PQFBC, RST_SRAM_ARBITER, RST_EMI, RST_PFQBC_AHB out of reset
__writeMemory32(0x00001053, 0x5C00201C, "Memory");
// SCU_SCR0 PFQBC enabled,SRAM_SIZE = 96kB
// DTCM & AHB wait-states disabled
__writeMemory32(0x00000191, 0x5C002034, "Memory");
}
难道问题在这里么?
难道问题在这里么?
为了在RAM调试, 需要先通过jtag使能内部的RAM
调试时先加载这个91x_ram.mac文件:
其中包含了这个设置函数:
execUserPreload()
{
__message "Enable 96KB RAM to download code ...
";
// SCU_CLKCNTR Fmstr = OSC, RCLK = Fmstr, HCLK = RCLK, PCLK = RCLK, BCLK = RCLK/2
__writeMemory32(0x00020002, 0x5C002000, "Memory");
// SCU_PWRMNG Power Mode = Run mode,
__writeMemory32(0x00000000, 0x5C00200C, "Memory");
// SCU_PCGR0 FMI, PQFBC, SRAM, SRAM_ARBITER, EMI, EXT_MEM_CLK clk enable
__writeMemory32(0x000000DB, 0x5C002014, "Memory");
// SCU_PRR0 RST_FMI, RST_PQFBC, RST_SRAM_ARBITER, RST_EMI, RST_PFQBC_AHB out of reset
__writeMemory32(0x00001053, 0x5C00201C, "Memory");
// SCU_SCR0 PFQBC enabled,SRAM_SIZE = 96kB
// DTCM & AHB wait-states disabled
__writeMemory32(0x00000191, 0x5C002034, "Memory");
}
把蓝色部分注释掉, 依然不能正常运行. 当中断发生了, 接着就是一直在
预取中止 里面死循环了.
通过把中断向量表放到ram低端, 可以解决问题
91x_vect.s 中的改动:
PROGRAM ?RESET
COMMON INTVEC:CODE(2)
CODE32
VectorAddress EQU 0xFFFFF030 // VIC Vector address register address.
VectorAddressDaisy EQU 0xFC000030 // Daisy VIC Vector address register
I_Bit EQU 0x80 // when I bit is set, IRQ is disabled
F_Bit EQU 0x40 // when F bit is set, FIQ is disabled
//*******************************************************************************
// Import the __program_start address from 91x_init.s
//*******************************************************************************
IMPORT __program_start
//*******************************************************************************
// Import exception handlers
//*******************************************************************************
IMPORT Undefined_Handler
IMPORT SWI_Handler
IMPORT Prefetch_Handler
IMPORT Abort_Handler
IMPORT FIQ_Handler
PUBLIC CopyStart
PUBLIC CopyEnd
//*******************************************************************************
// Exception vectors at Boot Flash 0x00000000
//*******************************************************************************
LDR PC, Reset_Addr // @0x00000000
LDR PC, Undefined_Addr // @0x00000004
LDR PC, SWI_Addr // @0x00000008
LDR PC, Prefetch_Addr // @0x0000000C
LDR PC, Abort_Addr // @0x00000010
LDR PC, Reserve_Addr // @0x00000014
LDR PC, IRQ_Addr // @0x00000018
LDR PC, FIQ_Addr // @0x0000001C
Reset_Addr DCD __program_start // @0x00000020
Undefined_Addr DCD 0x04000004 // @0x00000024
SWI_Addr DCD 0x04000008 // @0x00000028
Prefetch_Addr DCD 0x0400000C // @0x0000002C
Abort_Addr DCD 0x04000010 // @0x00000030
Reserve_Addr DCD 0x04000014 // @0x00000034
IRQ_Addr DCD 0x04000018 // @0x00000038
FIQ_Addr DCD 0x0400001C // @0x0000003C
//*******************************************************************************
// Exception vectors at RAM 0x04000000 : Copy from 0x00000040 : 64 Bytes
//*******************************************************************************
CopyStart LDR PC, Reset_Addr_RAM // @0x00000040 To 0x04000000
LDR PC, Undefined_Addr_RAM // @0x00000044 To 0x04000004
LDR PC, SWI_Addr_RAM // @0x00000048 To 0x04000008
LDR PC, Prefetch_Addr_RAM // @0x0000004C To 0x0400000C
LDR PC, Abort_Addr_RAM // @0x00000050 To 0x04000010
LDR PC, Reserve_Addr_RAM // @0x00000054 To 0x04000014
LDR PC, IRQ_Addr_RAM // @0x00000058 To 0x04000018
LDR PC, FIQ_Addr_RAM // @0x0000005C To 0x0400001C
Reset_Addr_RAM DCD __program_start // @0x00000060 To 0x50017FE0
Undefined_Addr_RAM DCD UndefinedHandler // @0x00000064 To 0x50017FE4
SWI_Addr_RAM DCD SWIHandler // @0x00000068 To 0x50017FE8
Prefetch_Addr_RAM DCD PrefetchAbortHandler // @0x0000006C To 0x50017FEC
Abort_Addr_RAM DCD DataAbortHandler // @0x00000070 To 0x50017FF0
Reserve_Addr_RAM DCD __program_start // @0x00000074 To 0x50017FF4
IRQ_Addr_RAM DCD IRQHandler // @0x00000078 To 0x50017FF8
FIQ_Addr_RAM DCD FIQHandler // @0x0000007C To 0x50017FFC
CopyEnd
//*******************************************************************************
// --- Copy Interrupt Vector Table to RAM : 64 bytes 0x04000000..0x0400003F
//*******************************************************************************
// LDR R0, =CopyStart
// LDR R1, =0x04000000
// LDMIA R0!, {R4-R11}
// STMIA R1!, {R4-R11}
// LDMIA R0!, {R4-R11}
// STMIA R1!, {R4-R11}
//*******************************************************************************
//* Function Name : FIQHandler
//* Description : This function is called when FIQ exception is entered.
//* Input : none
//* Output : none
//*******************************************************************************
FIQHandler
SUB lr,lr,#4 // Update the link register.
STMFD sp!,{r0-r7,lr} // Save The workspace plus the current return
// address lr_fiq into the FIQ stack.
ldr r0,=FIQ_Handler
ldr lr,=FIQ_Handler_end
bx r0 //Branch to FIQ_Handler.
FIQ_Handler_end:
LDMFD sp!,{r0-r7,pc}^// Return to the instruction following...
// ...the exception interrupt.
91x_init.s 改动:
EXTERN CopyStart
CODE32
//*******************************************************************************
// --- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,
// when the bank 0 is the boot bank, then enable the Bank 1.
//*******************************************************************************
LDR R6, =0x54000000 //
;LDR R7, =0x0 // BOOT BANK Size = 32KB : (2^0) * 32 = 32KB
LDR R7, =0x4 // BOOT BANK Size = 512KB : (2^4) * 32 = 512KB
STR R7, [R6]
LDR R6, =0x54000004 //
;LDR R7, =0x6 // NON BOOT BANK Size = 512KB : (2^6) * 8 = 512KB
;LDR R7, =0x2 // NON BOOT BANK Size = 32KB : (2^2) * 8 = 322KB
LDR R7, =0x3 // NON BOOT BANK Size = 32KB : (2^2) * 8 = 322KB
STR R7, [R6]
LDR R6, =0x5400000C // BOOT BANK Address = 0x0
LDR R7, =0x0
STR R7, [R6]
// 512KB Align
LDR R6, =0x54000010 // NON BOOT BANK Address = 0x80000
LDR R7, =0x20000 // need to put 0x20000 because FMI bus on A[25:2] of CPU bus
STR R7, [R6]
// --- Enable CS on both banks
LDR R6, =0x54000018
LDR R7, =0x18
STR R7, [R6]
// --- Enable 96K RAM
LDR R0, = SCRO_AHB_UNB
LDR R1, = 0x0191 // PFQBC enabled / DTCM & AHB wait-states disabled
STR R1, [R0]
//*******************************************************************************
// --- Copy Interrupt Vector Table to RAM : 64 bytes 0x04000000..0x0400003F
//*******************************************************************************
LDR R0, =CopyStart
LDR R1, =0x04000000
LDMIA R0!, {R4-R11}
STMIA R1!, {R4-R11}
LDMIA R0!, {R4-R11}
STMIA R1!, {R4-R11}
// --- Initialize Stack pointer registers
// ---Enter each mode in turn and set up the stack pointer
MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit // No interrupts
LDR SP, =SFE(FIQ_STACK) & 0xFFFFFFF8
为了在flash中调试代码, linker confing 修改:
// Code memory in flash
-DROMSTART=0x00000000
-DROMEND=0x0007FFFF
// Data memory
-DRAMSTART=0x4000040 //保留开始的64字节
-DRAMEND=0x4017FFF
为了在RAM调试 :
// Code and data in RAM
-DRAMSTART=0x04000040 //保留开始的64字节
-DRAMEND=0x04017FFF
// Code memory in RAM
-DROMSTART=RAMSTART
-DROMEND=RAMEND
提供相关文件仅供参考:
1. 首先在flash调试, 把代码写入boot flash, 然后可以
2. 在RAM调试了
相关链接:
https://bbs.eeworld.com.cn/upfiles/img/20071/200711714444117.rar
整个usb demo的项目文件, 仅供参考.
1. 其中P6.7 为低, usb 上拉电阻连接
其中P6.7 为高, usb 上拉电阻断开
2. P6.4 P6.5 两个pin作为输入, 移动鼠标指针.
相关链接:
https://bbs.eeworld.com.cn/upfiles/img/20071/2007117141154233.rar
京公网安备 11010802033920号
