[讨论] 招聘 Senior ASIC/FPGA Designer

一家北欧外企 招聘Senior ASIC/FPGA Designer， 招聘要求如下：

Job description

·         You will be an important person in our HW team, participate in ASIC and/or FPGA design for our in-house project, or on-site support for customer project.

·         You will work with the complete ASIC/FPGA design chain including pre-study, system design, implementation, verification and maintenance.

Technical Skills

·         Very good experience in VHDL/Verilog/SystemVerilog.

·         Very good understanding of ASIC and/or FPGA design flow.

·         Experienced in Xilinx or Altera FPGA and tools.

·         Experienced in one or more of the following areas is a plus:

o   Wired network technologies like E1, SONET/SDH, PDH, EoS, MEF, PON, IP Access Aggregation, ATM

o   Wireless telecommunication standards like GSM, CDMA, WCDMA, WiMAX, TD-SCDMA or LTE

·         Good understanding and experience of SOC design including high speed interfaces.

·         Experienced in scripting like Perl, Shell or TCL

·         Experienced with CM tools like Clearcase

Other qualifications:

·         B.Sc in Electronic Engineering or similar

·         At least 3 years professional experience

·         Strong analytical and problem solving skills

·         Self-motivated, achievement oriented and a good team player

·         Good command of oral and written English & Chinese

·         Can travel for 3~6 months, domestic or overseas

大家如果觉得合适，请把简历发给我，我是负责面试的负责人，如果条件符合的话，可以很快发offer.

联系邮箱：qylsmart@163.com