fpga_pwm

我这里用了飞思卡尔公司的verilog hdl coding semiconductor reuse standard 文档中的

head file格式。

// +FHDR------------------------------------------------------------------------
// Copyright (c) 2011 Guangxi Normal University Http://www.gxnu.edu.cn/
// -----------------------------------------------------------------------------
// FILE NAME      : pwm_top
// DEPARTMENT     : College of Electronic Engineering Innovation Base
// AUTHOR         : wall_e
// AUTHOR'S EMALL : li_junyi@foxmail.com
// RELEASE HISTORY
// VERSION DATA       AUTHOR DESCRIPTION
// 1.0     2011-08-15 Student
// -----------------------------------------------------------------------------
// KEYWORDS    : General file seraching keywords, lesve blank if none.
// -----------------------------------------------------------------------------
// PURPOSE     : pwm_logic project top level file.
// -----------------------------------------------------------------------------
// PARAMETERS
//     PARAM NAME    RANGE   : DESCRITPION       : DEFAULT : UNITS
//
// -----------------------------------------------------------------------------
// REUSE ISSUES
//   Reset Strategy      : There is no reset signal.
//   Clock domains       : clk_50mhz
//   Critial Timing      :
//   Test Features       :
//   Asynchronous I/F    :
//   Scan Methodology    :
//   Instantiations      :
//   Synthesizable (y/n) : Y
//   Other               : Reference to ZLG(Inc) book of <<EDA实验与实践>>
// -FHDR------------------------------------------------------------------------
module pwm_top(
               //input port
               sys_clk, //system clock 50mhz
               //output port
               pwm_out  //pwm signal output port
               );
input sys_clk; //input from the top
output pwm_out; //output to the top

wire[17:0] counter;
pwm_test pwm_test(
                  //input port
                  .sys_clk(sys_clk),      //input from the top
                  .counter(counter),      //input from pwm_logic
                  //output port
                  .pwm_en(pwm_en),        //output to pwm_logic
                  .duty_cycle(duty_cycle) //output to pwm_logic
                  );

wire pwm_en;
wire[17:0] duty_cycle;
pwm_logic pwm_logic(
                    //input port
                    .sys_clk(sys_clk),       //input from the top
                    .pwm_en(pwm_en),         //input from pwm_test
                    .duty_cycle(duty_cycle), //input from pwm_test
                    //output port
                    .counter(counter),       //output to pwm_test
                    .pwm_out(pwm_out)        //output to the top
                    );

endmodule

 

// +FHDR------------------------------------------------------------------------
// Copyright (c) 2011 Guangxi Normal University. Http://www.gxnu.edu.cn/
// -----------------------------------------------------------------------------
// FILE NAME      : pwm_logic
// DEPARTMENT     : College of Electronic Engineering Innovation Base
// AUTHOR         : wall_e
// AUTHOR'S EMALL : li_junyi@foxmail.com
// RELEASE HISTORY
// VERSION DATA       AUTHOR DESCRIPTION
// 1.0     2011-08-15 Student
// -----------------------------------------------------------------------------
// KEYWORDS    :
// -----------------------------------------------------------------------------
// PURPOSE     : Generate a  pwm signal.
// -----------------------------------------------------------------------------
// PARAMETERS
//     PARAM NAME    RANGE   : DESCRITPION       : DEFAULT : UNITS
// 
// -----------------------------------------------------------------------------
// REUSE ISSUES
//   Reset Strategy      : There is no reset signal.
//   Clock domains       : Clk_50mhz
//   Critial Timing      :
//   Test Features       :
//   Asynchronous I/F    : F
//   Scan Methodology    :
//   Instantiations      :
//   Synthesizable (y/n) : Y
//   Other               : Reference to ZLG(Inc) book of <<EDA实验与实践>>
// -FHDR------------------------------------------------------------------------
module pwm_logic(
                  //input port
                  sys_clk,  //system clock
                  pwm_en,     //pwm enable signal
                  duty_cycle, //duty control word
                  //output port
                  counter,
                  pwm_out     //pwm signal output port
                 );
input         sys_clk;   //input from pwm_top.v file
input[17:0]   duty_cycle;  //input from pwm_test.v file
input         pwm_en;      //input from pwm_test.v file  
output[17:0]  counter;     //output to pwm_test.v file
output        pwm_out;     //output to pwm_top.v file

reg       pwm_out;
reg[17:0] counter;

always @ (posedge sys_clk)
begin
    if(counter==249999)
        counter <= 0;      
    else
        counter <= counter + 1'b1;
end

//This processing will generate a fixation frequence
//which duty rate was control by duty_cycle.
always @ (posedge sys_clk)
begin
    if(pwm_en&(counter<duty_cycle))
        pwm_out <= 1'b1;
    else
        pwm_out <= 1'b0;
end

endmodule

 

// +FHDR------------------------------------------------------------------------
// Copyright (c) 2011 Guangxi Normal University Http://www.gxnu.edu.cn/
// -----------------------------------------------------------------------------
// FILE NAME      : pwm_test
// DEPARTMENT     : College of Electronic Engineering Innovation Base
// AUTHOR         : wall_e
// AUTHOR'S EMALL : li_junyi@foxmail.com
// RELEASE HISTORY
// VERSION DATA       AUTHOR DESCRIPTION
// 1.0     2011-08-15 Student
// -----------------------------------------------------------------------------
// KEYWORDS    : General file seraching keywords, lesve blank if none.
// -----------------------------------------------------------------------------
// PURPOSE     : Test pwm_logic.v file.
// -----------------------------------------------------------------------------
// PARAMETERS
//     PARAM NAME    RANGE   : DESCRITPION       : DEFAULT : UNITS
//
// -----------------------------------------------------------------------------
// REUSE ISSUES
//   Reset Strategy      : There is no reset signal.
//   Clock domains       : clk_50mhz
//   Critial Timing      :
//   Test Features       :
//   Asynchronous I/F    :
//   Scan Methodology    :
//   Instantiations      :
//   Synthesizable (y/n) : Y
//   Other               : Reference to ZLG(Inc) book of <<EDA实验与实践>>
// -FHDR------------------------------------------------------------------------
module pwm_test(
                 //input port
                 sys_clk,       //system clock
                 counter, 
                 //output port
                 pwm_en,        //pwm enable signal
                 duty_cycle     // duty control word
                );
input       sys_clk;     //input from pwm_top.v file
input[17:0] counter;     //
output      pwm_en;      //output to pwm_logic.v file
output[17:0] duty_cycle; //output to pwm_test.v file

reg[17:0] duty_cycle;

//每当 counter=249999时，duty_cycle自加700。
//在同频率不同占空比的情况下，led灯发光的程度是不一样的
//这里用counter控制占空比的变化，继而控制led灯由亮（占空比高）
//慢慢的变暗（占空比低），这一个过程是可视的。
always @ (posedge sys_clk)
begin
    if(counter==249999)
    begin
        duty_cycle <= duty_cycle + 700;
    end  
end

assign pwm_en = 1;

endmodule