| 我想做一个频率计 clk是信号， en是一个0.5hz的时钟， load=～en， clr=(load&~clk0(一个1hz的时钟）) module pi(clk,en,clr,load,c); input clk,en,clr,load; output [15:0]c; reg [3:0]a0;reg a_0; always @(posedge clk or posedge clr) begin if (clr) a0<=4'b0000; else if (en) begin if (a0==4'b1001) begin a0<=4'b0000;a_0=1;end else a0<=a0+1'b1;end end reg [3:0]a1;reg a_1; always @(posedge a_0 or posedge clr) begin if (clr) a1<=4'b0000; else if (en) begin if (a1==4'b1001)begin a1<=4'b0000;a_1<=1;end else a1<=a1+1'b1;end end reg [3:0]a11;reg a_11; always @(posedge a_1 or posedge clr ) begin if (clr) a11<=4'b0000; else if (en) begin if (a11==4'b1001)begin a11<=4'b1001;a_11<=1;end else a11<=a11+1'b1;end end reg [3:0]a3; always @(posedge a_11 or posedge clr) begin if (clr) a3<=4'b0000; else if (en) begin if (a3==4'b1001) a3<=4'b0000; else a3<=a3+1'b1;end end reg [15:0]c; always @(posedge load ) begin if (load )c<={a3,a11,a1,a0}; end endmodule 这是我写的程序，clk的频率一旦超过1.5khz就显示为1900； 小于1.5khz的话误差很大，请问一下是啥问题 |
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