[求助] 关于1个VHDL 编译错误

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;
LIBRARY lpm;
USE lpm.lpm_components.all;

ENTITY test IS
        GENERIC (MIO_TOTAL : INTEGER :=64 );        --考虑到IO输入点少1个，64-1=63
        PORT(
        osc_clk                : IN STD_LOGIC;   ---local端时钟信号
                -------------------
                io_output: buffer std_logic_vector(7 downto 0)

        );
      
END test;


ARCHITECTURE rtl OF test IS





        SIGNAL io_tog: STD_LOGIC_VECTOR (7DOWNTO 0):="01001000";
--        SIGNAL io_tog: STD_LOGIC;


begin

io_output<=io_tog SLA 0;



end rtl;

编译时出现 can't determine definition of operator ""sla""--found 0 possible definitions
这种是什么错误  怎么解决

VHDL综合器不支持SLA这个符号！