补充。。
如果直接在EDK中添加ISE的FIFO软核的VHDL模版,会出现错误
ERROR:NgdBuild:604 - logical block 'u1' with type 'fifo_core' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file,
case mismatch between the block name and the edif or ngc file name, or the
misspelling of a type name. Symbol 'fifo_core' is not supported in target
'spartan3e'. 这个跟在ISE里用FIFO的VHDL模版代替NGC的错误是一样的。。求大神解决。。。