RT.
完整信息如下:
# ** Fatal: Attempting to load -nodebug design unit.
# Nodebug designs are not supported.
#
# Time: 0 ps Iteration: 0 Instance: /ddr3_example_sim File: ./../ddr3_example_sim.v
# FATAL ERROR while loading design
example是在Quartus II 13.0产生DDR3 IP的时候产生的例程。
仿真工具的版本是ModelSim PE Student Edition 10.2b
从来没遇到过的错误,求助啊!
谢谢大家