要用VHDL实现简易的自动售货机
仿真时发现信号 MONEY 是未知的。刚学VHDL 很多都不会,花了很多时间最后能编译了,但还是有问题。求好心人抽空看下,谢谢了
程序如下:
library ieee;
use ieee.std_logic_1164.all ;
entity vending_machine is
Port(
x,y,z,clk: in std_logic;
test: out integer range 0 to 100;
water,change: out std_logic);
end entity;
architecture design of vending_machine is
type state_name is (waiting, A,B,C,SET);
signal current_state, next_state: state_name;
signal money : integer range 0 to 200:=0;
begin
process(clk)
begin
if clk='1' and clk'event then
current_state<=next_state;
end if;
end process;
process(x,y,z)
variable temp: integer range 0 to 100:=0;
begin
if x ='1' then
money <= money+25;
elsif y ='1' then
money <= money+10;
elsif z ='1' then
money <= money+5;
ELSE money<=money;
end if ;
end process;
process(x,y,z,current_state)
begin
case current_state is
when waiting =>
if x ='1' then
next_state <=A;
elsif y ='1' then
next_state <=B;
elsif z ='1'then
next_state <=C;
else if money>75 then
next_state<=SET;
else next_state<=waiting;
end if;
end if;
when A=>
next_state<=waiting;
when B=>
next_state<=waiting;
when C=>
next_state<=waiting;
when others=>
next_state<=waiting;
end case;
end process;
process(current_state)
variable temp: integer range 0 to 100:=1;
begin
case current_state is
when waiting =>
water<='0';
change<='0';
test<=money;
when A=>
water<='0';
change<='0';
test<=1;
when B=>
water<='0';
change<='0';
test<=2;
when C=>
water<='0';
change<='0';
test<=3;
when others=>
water<='1';
change<='1';
test<=money;
end case;
end process;
end design;