Products that include a 2-wire bus such as I2C or SMBus（这是一个和I2C几乎完全一致的总线，PCIe里面就有） impose trade-offs between fast risetime, low power consumption, and noise immunity. Because the risetime for low-to-high transitions on such open-drain buses is determined by pull-up resistors and bus capacitance（这个是重点）, it’s difficult to maintain clean, fast edges as you add peripherals, routing traces, and connectors.
In some cases, a correct sizing of pull-up resistors gives a risetime fast enough for good noise immunity along with acceptable power consumption. But, larger systems with high bus capacitance or portable systems with stringent power requirements may require an active circuit to achieve shorter risetimes for an open-drain signal, Figure 1.
IC1 is a low-voltage level translator used here for its risetime-acceleration capability rather than as a translator. When IC1 sees a voltage rise on an I/O pin, it briefly turns on an internal strong pull-up (a p-FET), which quickly charges the parasitic bus capacitance. The accelerator circuit is then disabled after a short time, leaving only the internal 10 kΩ pull-up resistors (plus any external pull-ups) to maintain the high logic level.
This idea is tested using the circuit of Figure 2, in which discrete open-drain FETs drive two separate lines simultaneously.
Channel 1 is accelerated by IC1, and channel 2 is terminated with a simple pull-up resistor and the parasitic capacitance (C is the same for both lines). The effective pull-up resistance for IC1 is only 5 kΩ, because it includes internal 10 kΩ pull-up resistors on input and output (the I/O Vcc and I/O VL pins). Results are shown for the benign case of 110 pF (Figure 3),
and the maximum of 400pF allowed on an I2C bus (Figure 4). (Note the different time scales in these figures.)
To judge the advantage gained by the Figure 1 circuit, consider the clock speeds common for 2-wire buses: 100 kHz and 400 kHz. At 100 kHz, the period is 10 μsec, with only 5 μsec in the high state. Thus, the risetime for approximately 110 pF capacitance and a 5 kΩ pull-up resistance (Figure 3) is only 12% of the period (about 1.25 μsec).（其实上升时间大约等于2.2RC = 2.2*5K*110p=1.21us）
For those conditions the performance should be OK without risetime acceleration. For 400 pF of parasitic capacitance, however, the risetime is ~4 μsec (40% of the period), which is unacceptable in many 100 kHz systems. Using the Figure 1 circuit to accelerate rise time in a 400 pF system yields a 90% rise in 500 ns (only 5% of the 10 μsec period).
For a 400 kHz bus (giving a high state of 1.25 μsec in a 2.5 μsec period), the above conditions of 5 kΩ and approximately 110 pF allow a risetime of only 1.25 μsec, which is 50% of the period and generally unacceptable. Raising the capacitance to 400 pF yields a 5 μsec risetime (double the period), which is clearly unacceptable. Again, the Figure 1 circuit with approximately 110pF load capacitance gives a 90% risetime of 250ns (only 10% of the 2.5 μsec period), and with 400 pF the risetime is only about 500 nsec, or 20% of the period.
The use of IC1 as a risetime accelerator is one of several methods for solving risetime versus clock problems on a 2-wire bus. You can speed the risetime simply by lowering the pull-up resistance in some cases. Figure 1, however, offers a simple way to speed risetimes while improving noise immunity and minimizing power dissipation.
京公网安备 11010802033920号
