[讨论] 求助，使用Qsys生成DDR3 controller with UniPHY 出现错误

刚学FPGA，要用到DDR3，开发板DDR3控制实例。我用MegaWizard plug-in Manager更改了参数（主要是最大突发长度），重新生成，出现以下面错误，急用，求大神帮忙（我用的是quartus ii 13.0.1,Cyclone V系列FPGA，开发板Arrow SoCKit）
错误信息：Error: s0: Error during execution of "{D:/program files/altera/13.0sp1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: s0: Execution of command "{D:/program files/altera/13.0sp1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
全部信息：

Info: Saving generation log to E:/SoCKit_DDR3/DDR3_generation_1.rpt
Info: Starting: Create block symbol file (.bsf)
Info: ip-generate --project-directory=E:/SoCKit_DDR3/ --output-directory=E:/SoCKit_DDR3/DDR3/ --report-file=bsf:E:/SoCKit_DDR3/DDR3.bsf --system-info=DEVICE_FAMILY="Cyclone V" --system-info=DEVICE=5CSXFC6D6F31C8ES --system-info=DEVICE_SPEEDGRADE=8_H6 --component-file=E:/SoCKit_DDR3/DDR3.qsys
Progress: Loading SoCKit_DDR3/DDR3.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 13.0]
Progress: Parameterizing module clk_0
Progress: Adding mem_if_ddr3_emif_0 [altera_mem_if_ddr3_emif 13.0]
Progress: Parameterizing module mem_if_ddr3_emif_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Warning: DDR3.mem_if_ddr3_emif_0: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors
Warning: DDR3.mem_if_ddr3_emif_0: mem_if_ddr3_emif_0.avl must be connected to an Avalon-MM master
Warning: DDR3.mem_if_ddr3_emif_0: mem_if_ddr3_emif_0.status must be exported, or connected to a matching conduit.
Warning: DDR3.mem_if_ddr3_emif_0: mem_if_ddr3_emif_0.pll_sharing must be exported, or connected to a matching conduit.
Info: ip-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
Info: ip-generate --project-directory=E:/SoCKit_DDR3/ --output-directory=E:/SoCKit_DDR3/DDR3/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:E:/SoCKit_DDR3/DDR3.sopcinfo --report-file=html:E:/SoCKit_DDR3/DDR3.html --report-file=qip:E:/SoCKit_DDR3/DDR3/synthesis/DDR3.qip --report-file=cmp:E:/SoCKit_DDR3/DDR3.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone V" --system-info=DEVICE=5CSXFC6D6F31C8ES --system-info=DEVICE_SPEEDGRADE=8_H6 --component-file=E:/SoCKit_DDR3/DDR3.qsys --language=VERILOG
Progress: Loading SoCKit_DDR3/DDR3.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 13.0]
Progress: Parameterizing module clk_0
Progress: Adding mem_if_ddr3_emif_0 [altera_mem_if_ddr3_emif 13.0]
Progress: Parameterizing module mem_if_ddr3_emif_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Warning: DDR3.mem_if_ddr3_emif_0: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors
Warning: DDR3.mem_if_ddr3_emif_0: mem_if_ddr3_emif_0.avl must be connected to an Avalon-MM master
Warning: DDR3.mem_if_ddr3_emif_0: mem_if_ddr3_emif_0.status must be exported, or connected to a matching conduit.
Warning: DDR3.mem_if_ddr3_emif_0: mem_if_ddr3_emif_0.pll_sharing must be exported, or connected to a matching conduit.
Info: DDR3: Generating DDR3 "DDR3" for QUARTUS_SYNTH
Info: pipeline_bridge_swap_transform: After transform: 2 modules, 5 connections
Info: No custom instruction connections, skipping transform
Info: No Avalon connections, skipping transform
Info: merlin_translator_transform: After transform: 2 modules, 5 connections
Info: pipeline_bridge_swap_transform: After transform: 17 modules, 39 connections
Info: No custom instruction connections, skipping transform
Info: merlin_translator_transform: After transform: 19 modules, 45 connections
Info: merlin_mm_transform: After transform: 19 modules, 45 connections
Info: mem_if_ddr3_emif_0: "DDR3" instantiated altera_mem_if_ddr3_emif "mem_if_ddr3_emif_0"
Info: pll0: "mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_pll "pll0"
Info: p0: Generating clock pair generator
Info: p0: Generating DDR3_mem_if_ddr3_emif_0_p0_altdqdqs
Info: p0:
Info: p0: *****************************
Info: p0:
Info: p0: Remember to run the DDR3_mem_if_ddr3_emif_0_p0_pin_assignments.tcl
Info: p0: script after running Synthesis and before Fitting.
Info: p0:
Info: p0: *****************************
Info: p0:
Info: p0: "mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_phy_core "p0"
Info: m0: "mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_afi_mux "m0"
Error: s0: Error during execution of "{D:/program files/altera/13.0sp1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: s0: Execution of command "{D:/program files/altera/13.0sp1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: s0: ]2;Altera Nios II EDS 13.0sp1 [gcc4]D:/program files/altera/13.0sp1/quartus/bin/uniphy_mcc -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../DDR3_mem_if_ddr3_emif_0_s0_AC_ROM.hex -inst_rom ../DDR3_mem_if_ddr3_emif_0_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_MR0=0001000100001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100100000 -DAC_ROM_MR1=0000001000110 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0001000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001001000001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001011000000 -DAC_ROM_MR1_MIRR=0000000100110 -DAC_ROM_MR2_MIRR=0001000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0
Error: s0: UniPHY Sequencer Microcode Compiler
Error: s0: Copyright (C) 1991-2010 Altera Corporation
Error: s0: Info: Reading sequencer_mc/ac_rom.s ...
Error: s0: Info: Reading sequencer_mc/inst_rom.s ...
Error: s0: Info: Writing ../DDR3_mem_if_ddr3_emif_0_s0_AC_ROM.hex ...
Error: s0: Info: Writing ../DDR3_mem_if_ddr3_emif_0_s0_inst_ROM.hex ...
Error: s0: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: s0: Info: Writing sequencer/sequencer_auto_inst_init.c ...
Error: s0: Info: Writing sequencer/sequencer_auto.h ...
Error: s0: Info: Writing sequencer/sequencer_auto.h ...
Error: s0: Info: Writing ../sequencer_auto_h.sv ...
Error: s0: Info: Microcode compilation successful
Error: s0: D:/program files/altera/13.0sp1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: s0: child process exited abnormally
Error: s0: Cannot find sequencer/sequencer.elf
Error: s0: An error occurred
    while executing
"error "An error occurred""
    (procedure "_error" line 8)
    invoked from within
"_error "Cannot find $seq_file""
    ("if" then script line 2)
    invoked from within
"if {[file exists $seq_file] == 0} {
                _error "Cannot find $seq_file"
        }"
    (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
    invoked from within
"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""
    invoked from within
"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"
    ("if" then script line 2)
    invoked from within
"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
                set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."
    (procedure "generate_qsys_sequencer_sw" line 777)
    invoked from within
"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name $ac_rom_init_file_name ..."
    invoked from within
"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0  $nios_hex_file_name ..."
    ("if" else script line 2)
    invoked from within
"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {
                set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."
    (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 195)
    invoked from within
"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"
    invoked from within
"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"
    (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
    invoked from within
"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"
    invoked from within
"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {
                set file_name [file tail $genera..."
    (procedure "generate_synth" line 8)
    invoked from within
"generate_synth DDR3_mem_if_ddr3_emif_0_s0"
Info: s0: "mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_qseq "s0"
Error: Generation stopped, 6 or more modules remaining
Info: DDR3: Done DDR3" with 12 modules, 33 files, 675758 bytes
Error: ip-generate failed with exit code 1: 20 Errors, 4 Warnings
Info: Finished: Create HDL design files for synthesis

是不是我的软件安装有问题啊？求解

过来瞧瞧啊  哈哈哈

重新安装quartus ii 13.1,就可以了，应该是软件破解问题，唉，浪费了我许多时间。

为什么我这边编译的时候出现ddr3 derive没有产生。。这是个什么情况，，，求指导啊，，

还有那个ip核时钟引脚分配成差分的 时候有ck和ck(n),ck_n(ck_n),而我们只需要两根差分时钟线，这边自动加了两个引脚。。要怎么连接

你好，大哥，我现在也想在带有HPS的FPGA中调用一个DDR3控制器，苦于界面配置的一些参数不知道怎么样设置，可以请教一下你吗？